NPU startup shifts focus to Ethernet

In an announcement Monday (April 28) at Networld+Interop here, the company unveiled two processor, the X10q-e and X10q-m, optimized for Ethernet designs while also saying that it will phase out two lower-density Sonet parts—the X10s and X10d.

Like the original X10q, which has now been renamed the X10q-w, the X10q-e and X10q-m provide four SPI 4.2-enabled receive paths, four SPI 4.2-enabled transmit paths, and a programmable data path. The processors also offer four look-aside interfaces for linking up with SRAMs, ternary content-addressable memories (TCAMs) or co-processors. Four on-chip engines are also provided for metering, hashing functions, TCAM operations and counting.

The X10q-e is targeted solely at Ethernet designs and delivers a 60-Mpps packet rate and a 6.5-W power dissipation figure. The X10q-m, on the other hand, can be employed in Ethernet or Sonet designs and delivers a 90-Mpps packet rate and a 10-W dissipation figure. The X10q-w, which sports a 100-Mpps packet rate and 11-W power dissipation figure, will remain focused at the Sonet market. All three parts are developed in a 0.13-micron process.

Xelerated has received the first silicon for its X10 parts. The parts will be on display at the N+I show this week.