News & Analysis
Integration for Performance
2/10/2003 7:27 AM EST
Integration for Performance
Adding net functions to GHz chips
Researchers scale power barrier at ISSCC
Moving to the GHz plus range in SoC design?
Integration by function puts more features, interfaces into handsets
Keeping leakage current under control
Global strategy needed for integrating IP in complex SoC design
Reaching for the 1 GHz ring
Burning rubber on the SoC freeway
Trading off performance for power has never been an easy task. This week we'll take a
look at how some developers are managing to juggle the gigahertz-performance requirements
of today's huge system-on-chip designs and the demands those systems make on power consumption.
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