News & Analysis
SOC Road Map
1/13/2003 9:41 AM EST
SOC Road Map
Adapting an architecture to fit 130 nm
Async chip design eases process shift
Advanced library format "attacks" advanced design issues
1T-SRAM improves yield, benefits SoCs
Next generation SoCs: optimized IP platforms
Lessons learned from extending 0.12 µm CMOS for multimillion gate, IP designs
Taking on the 130nm node and beyond
Software takes center stage to meet vital SoC goals
Future success of SoCs and platforms lies in verification<
SoC technical difficulties ahead; stand by
Despite the assurances of foundries, ASIC vendors and tool suppliers that the problems
with 130-nanometer CMOS are well in hand and that 90 nm is ready to use, there is a rumbling
of voices from experienced design teams that not all is well.
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