Simulating the XFP Electrical Interface: Part 1

Designers of optical networking and Gigabit Ethernet equipment are faced with a myriad of module options. From Xenpak to XFP to X2, choosing the right module architecture could be a daunting task.

Despite all the options, the XFP module is capturing quite a bit of attention in the sector. By leaving the transceiver off the module, XFP is seen as delivering the small size and flexibility needed in today's communication sector.

With the transceiver on the host board, it becomes necessary to transmit 10Gb/s data signals across 8 to 12 in. spans of lossy FR-4 PCB. Design of the high-speed interconnect on these boards requires special attention to ensure signal fidelity. Electromagnetic (EM) field simulations can help, especially for complex 3D geometries. Through EM simulations designers can more accurately analyze the electrical performance of the connector, BGA packages, and circuit traces.

In this two-part series, we'll look at some key EM simulations that designers can use to evaluate the electrical performance of an XFP module system. In Part 1, we'll provide an overview of the spec and look at simulations for the microstrip traces. In Part 2, we'll look at the connector, the BGA package, and the system-level end-to-end performance.

XFP: An Overview
The XFP multisource agreement (MSA) group was founded in late 2001 to define a 10 Gbit/s serial transceiver for datacom and telecom applications. The XFP group consists of leading networking, system, optical module, semiconductor and connector companies from both the datacom and telecom industries. Founding member companies include Broadcom Corporation, Brocade, Emulex Corporation, Finisar, JDS Uniphase, Maxim Integrated Products, ONI Systems, ICS (a Sumitomo Electric company), Tyco Electronics and Velio. Presently, there are over 60 companies specializing in optics, ICs, and system implementation that have joined the XFP MSA as contributors and adopters (see www.xfpmsa.org for more information).

The XFP module is a hot-pluggable, serial-to-serial optical transceiver that supports Sonet OC-192, 10 Gigabit Ethernet, 10-Gbit/s Fibre Channel, and G.709 links. Figure 1 is a drawing of a typical XFP module. The module is 78 mm in length, 18.4 mm in width, and 8.5 mm in height. This small size is afforded by the fact that the majority of electronic signal processing has been located in devices on the host board rather than within the module.

Older form factors like XENPAK and the telecom 300-pin XBI modules were specified with XAUI transceivers and mux/demux devices, respectively, that increased the size, complexity, and power requirements. The new XFP form factor is four times smaller than Xenpak allowing up to 16 ports per linecard. XFP uses two times less power (depending upon application) with implementations that require as little as 1.5 Watts.

The new XFP form factor features a serial 10 Gbit/s electrical interface called XFI that places the majority of electronic signal processing functions within the transceiver ASIC on the system printed circuit board rather than within the optical transceiver module. Because electronic processing defines the communication protocol, the XFP module is protocol independent allowing volume production and attendant lower cost. It is generally expected that XFP will dominate the optical transceiver markets for datacom and telecom applications due to the overwhelming advantages it offers.

Placing the transceiver ASIC on the system printed circuit board (PCB) creates a significant challenge for system designers to implement 10Gbit/s serial interfaces on traditional FR-4 printed circuit boards (PCBs). Special care must be taken to ensure that the interface supports sufficient signal amplitude and fidelity after traversing 8 to 12 in. of PCB interconnect. The interconnect may include combinations of microstrip and/or stripline traces, layer-to-layer via structures, a 30-pin connector, and a BGA ASIC package.

Geometries of connectors and BGA packages are generally complex making it impossible to calculate their electrical performance without the assistance of electromagnetic (EM) field simulation or measurements. Similarly, formulas for characteristic impedance, effective dielectric constant, and loss of transmission line structures, while useful for preliminary design, should be augmented by EM field simulation for the most accurate results.

Below we'll provide simulation examples for circuit traces, the XFP 30-pin connector, and a BGA package using two- and three-dimensional EM field solvers. Models extracted from simulations provide frequency- and time-domain responses of the interconnect components. Models are cascaded using system simulator software to produce channel frequency response and eye diagrams. These examples demonstrate that application of simulation software can accelerate successful design for XFP adopters.

Simulating the Electrical Channel
The XFI interface is a differentially signaled, serial interconnect with nominal baud rate between 9.95 and 10.75 Gbit/s. Transmit and receive signals are AC coupled, 100-ohm differential pairs. The interconnect may include combinations of microstrip and/or stripline traces up to 12 in. (300 mm) in length, layer-to-layer via structures, a 30-pin connector, and a BGA ASIC package.

Figure 2 depicts a typical system block diagram of an end-to-end electrical channel for XFP applications. This XFI channel will be used for several examples in this article. The block diagram includes a transceiver board that exists within the XFP module, a 30-pin hot swappable connector, a host board, and a BGA package. Although most host board designers will not have any direct control over the transceiver ASIC BGA package, it is nevertheless important to include the package in channel simulations to understand the end-to-end performance.

Simulations and measurements of XFI electrical channel are discussed to provide guidelines on XFP design. Broadcom Corporation provided the transceiver and host boards and electrical measurements; Tyco provided the connector model, ASAT provided the BGA package model; Ansoft Corporation performed simulations.

Microstrip Traces
The most prominent feature of the XFI interface is the attenuation of the transmitted signal across the PCB. PCBs with FR-4 dielectric substrates were never intended to support signals at 10 Gbit/s; the dielectric loss at high frequency is very pronounced and provides the dominant impairment. Typical microstrip differential transmission lines on FR-4 exhibit insertion loss of roughly 0.5 dB/in. at 5 GHz and 0.9 dB/in. at 10 GHz. This loss effectively performs a low-pass filtering of the transmitted digital signals and hence severely limits the distance that uncompensated gigabit/second digital signals can propagate on PCB transmission lines. Fortunately, modern signal conditioning circuits in the transceiver ASICs and within the XFP modules can compensate for this filtering and enables transmission distances up to 12 in.

The challenge that remains for the host board designer is to provide transmission lines with the proper characteristic impedance and routing, and via designs that have sufficiently low return loss. In the discussion that follows, we'll discuss PCB loss mechanisms with some emphasis on the relative signal attenuations due to dielectric and conductor loss. Circuit and electromagnetic analysis is performed to illustrate the additional accuracy provided by modern software design tools.

Figure 3 depicts a typical differential microstrip transmission line on an FR-4 substrate with material parameters of ε_r= 4.2 and tanδ = 0.022. The traces are 1/2-ounce copper, 8-mils wide with a gap between them of 8-mils; the substrate height is 6 mils. This geometry provides a nominal 100-ohm characteristic impedance.

Simulations using a 2D fullwave finite element method (FEM) field solver were performed to extract the propagation and attenuation constants. Results from these simulations are depicted in Figure 4.

The results shown in Figure 4 are expressed in terms of the propagation constant and hence loss is reported in Nepers/meter (Np/m). One can convert to decibels by multiplying by 8.686 dB/Np.

As designers can easily see from Figure 4, signal attenuation due to dielectric loss is significantly greater than the conductor loss. At 10 GHz, for example, the dielectric loss is 4X greater than the conductor loss. This is in stark contrast to the high-performance substrates that are used for microwave and RF designs. Typical low-loss substrates such as Rogers RT/duroid, and Taconic have loss tangents in the 0.001 to 0.002 range at 10 GHz. This corresponds to propagation loss on the order of 0.07 dB/in. at 10GHz as opposed to the 0.9 dB/in. of standard FR-4.

Circuit and EM Simulation
Rigorous examination of circuit traces on PCBs can be performed using combinations of high-frequency circuit and planar electromagnetic (EM) simulation. In general, the EM simulations are the most rigorous and hence are considered most accurate. Circuit simulations are generally faster and provide sufficient accuracy as long as modeling rules are maintained.

Figure 5 depicts the simulation options when evaluating the transceiver board shown in Figure 2. A system-level model may be obtained using pure circuit simulation, pure EM simulation, or combinations thereof.

In circuit simulation, models of particular trace geometries are assembled in a schematic format. For the differential traces of XFI, it is important to utilize a coupled-line model for traces that are closely coupled. Since most circuit simulators do not include models for coupled line bends, an appropriate design practice is to use EM simulation for these elements and circuit models for the rest.

Figure 6 depicts simulation results for the six-layer transceiver board shown in Figure 2. Total board thickness is 36 mils and the board material is standard FR-4 with ε_r = 4.0 and a loss tangent of 0.016. All traces are 0.5-oz. copper. Coupled line models have been used for all of the uniform transmission line sections; standard bend models were used at all trace other locations.

The results from Figure 6 show that combinations of circuit simulation plus EM simulation can virtually match pure EM simulation. Similar results were generated for the host board traces. Coupled line models were used for all of the uniform transmission line sections; standard bend models were used at all trace other locations.

On to Part 2
That wraps up Part 1 in our series on simulating the XFP electrical channel. In Part 2, we'll look at the connector, the BGA package, and the system-level end-to-end performance. To view Part 2, click here.

About the Authors
Lawrence Williams is director of business development at Ansoft Corp. He received his Masters, Engineers, and Ph.D. degrees from UCLA . Lawrence can be reached at williams@ansoft.com.

Steve Rousselle is an applications engineering manager at Ansoft Corp. He received a BSEE and MSEE degrees from Michigan Technological University. Steve can be reached at srousselle@ansoft.com

Bryan Boots is an application engineer at Ansoft Corp. He received a BSEE and MSEE from the University of Colorado, Boulder. Bryan can be reached at bboots@ansoft.com.