News & Analysis
High-Speed Interconnects
1/27/2003 8:27 AM EST
High-Speed Interconnects
Speed demands accurate models
Need for services displaces speed
Signal skew managed dynamically
Harnessing the power of high speed interconnects with software
Building the next-generation of extensible mesh fabrics
Next-generation backplanes: Are we talking 5Gig or 10Gig?
With StarFabric as an on-ramp, the PCI Express Advanced Switching is ready
Common I/O design strategies for high-speed interfaces
How to apply SERDES performance to your design
Royalty-free HyperTransport makes good on chip-to-chip bandwidth
10 Gbit/sec: Breaking down the system design issues
Designers ponder unified data transport era
Designers of multigigabit transceiver and serializer/deserializer chips have argued for nearly a decade
that, as backplanes, fabrics and in-system interconnects reach speeds of 2 to 10 Gbits/second,
the design problems will be similar whether the interconnect goal is interchip links,
unified backplanes or board-to-board I/O.
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