Next-generation backplanes: Are we talking 5Gig or 10Gig?

Many of the today's backplanes were developed with then state-of-the-art 2.5Gig or 3.125G serdes technology. Some of these systems support line card bandwidths up to 40 Gigabits per line card. The trend in line cards continues to move towards greater port densities and higher line rates.

With the rapidly declining cost, power, and size of optical modules, new line cards are possible that can support 8 Xenpak/Xpak or X2 modules and can even go to 16 ports of 10 Gigabits with upcoming XFP MSA solutions. These higher density line cards require backplane support from 80 to 160Gig/slot. But in order to future proof these systems, backplanes must move to new levels of bandwidth capacity. The real question is what is the next step, 5/6.25Gig or 10/12.5Gig?

Business models and strategies need to be considered when determining the right solution. For example, if a networking company has a large installed base of chassis-based systems in the market, it may want to offer its customer's an upgrade path on their legacy backplanes to extend the life and usability of their current system without having to forklift in a new chassis and open the door to competing solutions.

In today's cost-conscious market, this may be an attractive roadmap to offer the customers of its large installed base of systems. On the other hand, a new entrant in the market, whose only opportunity is to displace an existing chassis solution or add into existing requirements of a customer's growing IT needs may consider more aggressive system backplane designs to future proof their systems.

In each case the technology approach used to solve the backplane scaling or design problem face different challenges.

In any high-speed backplane design there are a number of design variables that come into play. These include, but are not limited to, dielectric material, board layers, vias — which act like high-speed stubs — connectors, trace lengths, channel spacing, and serdes technology. To a designer, these variables provide a significant number of challenges as well as a greater degree of flexibility to develop a high-speed backplane.

Getting high-speed signals over a backplane channel has some significant signal integrity challenges. Each channel is a point-to-point connection from a transmitting device to the receiving device. Each of these point-to-point connections (or channels) has different characteristics based on the different trace lengths, trace discontinuities, and possibly different neighboring channels that have coupling effects.

The transmitted signal is impaired by four key channel factors:

• Signal attenuation caused by voltage (IR) drop across the trace length. This is a predominant factor due to skin effect loss that is proportional to the square root of the frequency of the signal. It can be partly controlled by the trace cross sectional area used.

• Dielectric loss based on the signal energy leakage through the board dielectric material. This loss increases linearly with frequency. It can be partially controlled or minimized by using different materials like FR4 and Nelco.

• Cross-talk distortions caused by capacitive coupling of adjacent signals coming from near-end or far-end transmitted signals. This can be controlled by layout designs as well as using newer connector technologies. It can also be resolved by better receive equalization by the SerDes devices.

• Reflections can cause signal distortions due to impedance mismatches of the channel. This again can be controlled by trace layouts, connector technology, and impedance matching. Serdes transmit pre-emphasis and receive equalization technology can also be used to address reflections.

Legacy backplanes provide a limited amount of design freedom. Fixed backplane material, existing connectors and channel impedance characteristics are part of the "legacy" of the original design. Most have impedance models that may require very robust and complex signaling and/or adaptive equalization to offer hassle-free user upgrades to higher speeds.

In many cases, these constraints are huge barriers to getting higher line rates and providing cost-effective solutions to upgrades. Therefore, most legacy upgrades will be limited to 5 or 6.25Gig options. It is unlikely that attempting to achieve 10Gig line rates makes sense unless the legacy backplane has clean 10Gigabit channels in the original design. More complex and costly signaling technology may be required for the serdes to achieve even the 5 or 6.25Gig data rates. With these added complexities and costs,10Gig data rates may not be feasible.

New backplanes have more degrees of freedom and could provide better and more cost-effective results at higher speeds. Use of new dielectric materials, better connectors, and less costly serdes technology, now become options.

In legacy-based backplane designs, gradual upgrades to line cards add complexity to the switch fabric if interoperability is required with other legacy line cards Power, which is already a major concern, would most likely increase. This is not just because of the backplane serdes, but because the rest of the system would be scaling in bandwidth as well. There may be power limitations based on power supply and airflow constraints.

Some of the approaches provided by serdes technology may be faced with interoperability problems. Multi-level signaling, out-of-band signaling and adaptive equalization techniques are difficult to standardize.

Interoperability challenge

A big issue for system designers is interoperability between backplane serdes. Most system providers require multiple interoperable products for their serdes solutions. The need to be interoperable and provide a secured supply for their backplane solutions is mission-critical. And, of course, another requirement is to keep costs in line because of competitive products.

At higher speeds, transmission techniques need to adhere to some well-established standard in order to provide interoperability between different backplane interfaces on line cards that must communicate with each other or with a centralized switch fabric. As some of these functions become more integrated within switch fabrics, serial interconnect standards become incredibly important to ensure interoperability and design longevity.

Different transmission techniques have their trade-offs. Two more prominent approaches are Multi-Level Signaling (e.g. PAM4) vs NRZ. Depending on whether you are addressing a legacy backplane upgrade or a new backplane system design, these two approaches have specific advantages and disadvantages that must be weighed by the system designer. NRZ has been chosen by most of the high-speed serial transmission standards. Some PAM4 MLS implementations still have a great deal of non-standard out-of-band signaling required to take advantage of the equalization techniques.

Interoperability is preferred by the system designer in order to have a wide range of suppliers and therefore more competitive costs. However, once a designer has tested interoperability and has alternative solutions, it is rare that he will design the board to accommodate different pin-out solutions.

A chassis system designer must create a backplane solution that can scale to meet the future line card bandwidth requirements during the life of the system.

Designing an upgrade to a legacy backplane is one way to try to extend the life of a previous generation backplane that has run out of bandwidth for new competitive density line cards. This would be the case for going to 5 or 6.25G backplane solutions.

A new chassis system should attempt to future proof by developing the cleanest channel for transmission on the backplane. This involves careful design and selection of backplane materials and connectors, as well as careful layout of the backplane traces.

The next backplane solutions will undoubtedly be 10Gig. The biggest challenges are getting good transmission distances and keeping the power low. While the technology is being developed to solve these backplane issues, the rest of the system needs to be able to take advantage of the new channels. With the availability of high-speed serdes cores for ASICs and for ASSP chip-to-chip interfaces, the ability to develop a streamlined line card that can fully utilize and scale to the 10Gig backplanes is already here. The 5Gig or 6.25Gig backplane is a stopgap measure that will benefit the legacy backplane upgrades, but should not be the next-generation backplane target.