News & Analysis

NETWORKING: Synchronous Ethernet ICs lower line card/central timing costs

Toni McConnel

3/6/2009 12:15 AM EST

Ottawa, Canada -- The new ZL30143 and ZL30142 Synchronous Ethernet devices from Zarlink Semiconductor Inc. integrate analog and digital phase locked loops (APLL/DPLL) for central timing card applications in carrier-grade networking equipment.

The ZL30143 timing card device provides two independent DPLLs for applications that require independent transmit and receive timing paths, while the ZL30142 device uses a single DPLL for clock and/or frame pulse synchronization.

Delivering high performance at a low cost, the devices require only an inexpensive temperature controlled crystal oscillator (TCXO) to achieve full compliance with ITU-T Recommendation G.8262.

Zarlink also offers two new devices for line card applications. The ZL30146 chip incorporates two independently configurable DPLLs for PDH/SONET/SDH and Ethernet network interface cards requiring both transmit and receive paths.

The ZL30145 provides one DPLL for clock synchronization, and delivers rate conversion and jitter attenuation compliant performance for Synchronous Ethernet, SDH and SONET equipment. The devices require only off-the-shelf, low-cost 20 MHz oscillators or even a crystal, rather than an expensive high precision clock or high frequency rate oscillator.

Zarlink's Synchronous Ethernet solutions are designed to allow carriers to lower operating costs and increase revenue by ensuring accurate end-to-end transmission of voice, video, data and mobile applications and services over IP-based wired and wireless networks.

According to the company, Zarlink is the only supplier offering single-chip Synchronous Ethernet solutions in full compliance with the International Telecommunications Union (ITU-T) Recommendation G.8262, while supporting very low jitter clocks for both 1 GbE and 10 GbE PHYs.

For more information visit www.zarlink.com.





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