<b>The CTO interview</b> with Philips' Theo Claasen: Part II

In part two of an our CTO interview with Theo Claasen, chief technology officer of Philips Semiconductors, Peter Clarke asked about Nexperia and some of the design issues and networking challenges that face the system-on-chip.

Silicon Strategies: Four or five years ago the platform-based approach to developing chips was a research idea. It is now in use. Has it lived up to expectations?

Claasen: Our viewpoint was that consumer electronics would rapidly go digital, become increasingly feature-rich and be networked. We would have been forced to develop a large number of chips unless we could make them programmable. Programmability allows 'silicon-sharing' which can reduce power consumption because a piece of equipment capable of doing many things is often not required to do them at the same time.

Silicon Strategies: There's two types of programmability, software on a processor and hardware as in FPGA

Claasen: I think of hardware programmability as reconfigurability. Software programmability on a processor is what I meant although a microprocessor or microcontroller is not well-suited to streaming data which would dominate consumer goods. Which is why we pursued a CPU plus media processor or DSP.

Silicon Strategies: Another aspect of Nexperia was the restriction that designers should not design new cores or import third-party cores, but work from a limited set of platform cores.

Claasen: In the beginning it was an exercise to persuade departments that they should stick with the strict discipline. Some have deviated!

We are much more strict today because we have seen the delays it can cause. The end customer or the department think they can go faster to market by cutting corners or using a different core. But some have learned the hard way. We have seen now the benefits of software reuse. There are 40 telephones in the market based on Nexperia, most of them differentiated in software.

Silicon Strategies: So what comes next?

Claasen: We still need to push out the Nexperia concept. The 90-nanometer node allows much fuller integration. I think now we must learn how to make massive use of software for differentiation. As mask costs get more expensive you have to think more about whether you should make a small change to a die. Often the answer will be no.

Silicon Strategies: Will you introduce FPGA patches to allow hardware reconfiguration?

Claasen: Reconfigurability of design without going through mask charges is attractive.

Silicon Strategies: FPGA?

Claasen: There are some possible ways of doing processors with loadable instruction sets so that we can get closer to application-specific processors. So you can use reconfiguration can change the processor configuration. It is important to combine silicon efficiency with ease of programmability. We want to make processor cores more adaptable.

Also the question of whether a the bus structure is the right solution should be raised again; what we have is based on Ethernet with bus conflicts and arbitration. Network configuration packet messaging is more efficient or there may be other means; assuming a large number of autonomous traffics; TCP/IP on a chip could be one but it is designed for an asynchronous environment whereas the chip is likely to be plesiosynchronous.

Silicon Strategies: Talking about networks on chip, how will massively parallel processing be incorporated within Nexperia or its derivatives?

Claasen: Yes; it becomes economically feasible to put lots of computer engines on a chip. But that doesn't necessarily mean lots of ARM, MIPS or other CPU cores. Parallel processing can be used for streaming data but is better on a DSP or media CPU.

Silicon Strategies: There have been numerous start-up companies that have produced processor arrays based on compute engines of various sizes from a few bits in so-called associative string processing approach up through 4-, 8-, 16- and 32-bit processing engines

Claasen: Bit-level processing is decreasing in favor of 32-bit engines but one of the most important things is power management at the tile level. There will always be some tasks that don't require all resources and you have to be able to control the power.

One way to proceed is to introduce an intermediate layer of abstraction and define routines in terms of the cores or tiles that are required to run it.

Silicon Strategies: As these single chip machines become more complex the way they operate can seem to become undeterministic. It may not boot up the same way twice just because of the way memory gets loaded into caches and so on. Is that going to become a problem with testing and so on?

Claasen: Already our chips are non-deterministic. We have to cope with that. But non-determinism is not the same as unpredictability.

But we do need to think about how to deal with non-deterministic machines. Today's chips are beyond FSMs (finite state machines). Even if the number of states is finite it is too many. But there can be built-in mechanisms with a certain degree of responsiveness.

And we are no longer building stand-alone machines; they are interconnected.

In fact the telephone network behaves much better than a computer network does, because the telephone network was built with connectivity in mind.