News & Analysis
Motorola unveils first Star*Core DSP product
9/13/1999 10:52 AM EDT
AUSTIN, Tex. -- The first product based on the Star*Core digital signal processor core developed jointly by Motorola Inc. and Lucent Technologies Inc. was announced here today.
The MSC8101, based on Motorola's SC140 implementation of Star*Core, features an on-chip network interface supporting Asynchronous Transfer Mode (ATM), Fast Ethernet and fast TDM highways.
With a 300-MHz DSP core, the chip offers four arithmetic logic units (ALUs) providing 1,200 DSP MIPS or 3,000 RISC MIPS; a high-performance 150-MHz Communications Processor Module (CPM) programmable network protocol engine;512 kilobyte (256K 16-bit words) of on-chip SRAM; a 100 MHz 64- or 32-bit PowerPC bus interface; and a programmable memory controller.
On-chip peripherals such as a 300-MHz enhanced filter coprocessor (EFCOP) and a powerful centralized DMA engine push performance even higher.
"Our MSC8101 is the first chip to integrate the SC140 DSP core unveiled by the Star*Core alliance last April," said Daniel Artusi, vice president and general manager of Motorola's Networking and Computing Systems Group (see April 19 story). "This is a genuine breakthrough for performance-intensive applications in wireless and wireline infrastructure equipment such as Internet telephony gateways, next-generation digital cellular infrastructure systems, xDSL telephone equipment, and multi-channel modem banks.
The MSC8101 is manufactured using Motorola's new 0.13-micron copper interconnect process technology. It operates with a 1.5-volt core and an independent 3.3-V I/O power supply, dissipating about 500 mW of power for the entire device, all in a 17-x-17-mm plastic package.
With the MSC8101, Motorola is targeting the transition from circuit switched networks to packet switched networks. In addition to today's packetized data, tomorrow's system must handle packetized real-time streams such as speech and video. DSPs, which have always been optimized for real-time applications, will be required to interface to packetized backbones such as 155-bits-per-second ATM backplanes.
Motorola's new chip, equipped with its programmable 32-bit RISC CPM, runs the networking protocol layers, enabling the MSC8101 to link directly to packetized backbones, such as ATM and Fast Ethernet, as well as PCM highways such as E1/T1 and E3/T3.
Motorola claimed the MSC8101 is the first product to offer the combination of DSP, PowerPC, and CPM technologies in an integrated device.
"The MSC8101 consists of an extremely powerful DSP engine that has been married with Motorola's market-leading communications processor architecture and its widely-supported PowerPC bus," said DSP market watcher Will Strauss, president of Forward Concepts in Tempe, Ariz. "The MSC8101 opens the door for distributed systems where the DSP processes the data directly from the network stream."
Qualified customers can receive samples of the MSC8101 beginning in the second quarter of date for is 2000. Pricing is expected to be below $100.



