The Interview: Scott Kulicke

The Interview: Scott Kulicke
SAN JOSE--It's been nearly a half century since Fred Kulicke and Al Soffa started up Kulicke & Soffa Industries Inc. in Willow Grove, Penn. Today, both of them would be proud of Fred's son Scott, who is now busily refocusing the chip-packaging equipment giant to meet the major changes he sees coming in this market.

In many ways, C. Scott Kulicke wants his company--the world's largest supplier of backend chip-packaging equipment--to emulate the "complete solutions" strategy of Applied Materials Inc., world's largest supplier of frontend wafer fab tools.

Last year, the chairman and CEO refocused the 49-year-old company on delivering a range of chip-assembly systems, materials, and processes for backend packaging plants. And like Applied's ambitious efforts, Kulicke wants to ship technologies along with his fab gear.

K&S has been actively acquiring companies to fill out its technology and create new assembly processes. Known from the beginning as an innovator, the company was the first to sell semiconductor assembly systems in the mid-1950s. Now it is pushing hard to set the pace for change this decade.

Kulicke is convinced that the chip-packaging equipment segment will look much different in the future. Major suppliers will provide much more of the process technologies along with their hardware--just like the wafer fab tool providers, he said. He eventually expects to see a merging of the IC-tester business with the chip-packaging equipment segment.

Kulicke doesn't shy from controversy and at a meeting during the Semicon West conference here in July, he told editors that he was sure the industry's current boom period would not significantly slow down over the next couple of years.

But he does believe his customers will cause the next downturn by investing too much in chip-production capacity. He also called the "system-on-chip" over-hyped and predicted that 300-mm wafers wouldn't take off as fast experts are predicting.

Kulicke, who has been K&S chairman since 1984 and CEO since 1980, also has a lengthy reputation for pushing technology ahead faster in backend IC-packaging systems. As a young K&S product manager in the mid-1970s, he led the engineering team launching a computerized wire bonder that would dramatically change the company from a supplier of mechanical-based machines to a builder of automatic tools.

Here's how Kulicke answered editors' questions at Semicon West last month:

QUESTION: What are the mainstream drivers and challenges in semiconductor packaging and assembly today?

KULICKE: Most of technical challenges we deal with are natural offshoots from the semiconductor trend line of shrinking feature sizes. The obvious one is that as our customers shrink feature sizes, the bond pads scale down too. In wire-bond applications, that creates pad pitch issues spacings between pads. Therefore we talk about pad-pitch initiatives.

The less obvious issue that shrinking feature sizes creates are wire length issues and other issues upstream and downstream for our products in process steps for wafer probe, molding, and other processes. All of those things are under pressure with shrinks. We are always playing catch-up with what's going on in the wafer fab and trying to react to that.

There is a whole other trend line of technical pressures associated with reducing the footprint of silicon chip on printed-circuit boards. Chip-scale packaging is one manifestation. Direct chip attach to boards in handheld and portable applications is another. That creates handling problems, machine problems, and material-set problems.

There is no one big blockbuster issue. It is just a continued stream of issues that have to be tackled.

The third problem the industry faces is that backend assembly is incredibly cost sensitive as opposed to the wafer fab. People are always trying to get another tenth of a penny out of the unit here and there. Things like the LaserPro* launched at Semicon West in July are a response to those demands to reduce the cost of ownership or cost per aberration in IC packages. We get this mixed message from customers. They want more and more capability and, of course, the price has to go down.

*LaserPro is the new K&S laser solder sphere attachment tool for high-volume, ultra-fine pitch plastic ball grid arrays (BGAs).

QUESTION: What is the bond pad pitch limit for wire bonding?

KULICKE: I'm going to give a 'lawyerly' answer to that: It depends.

First, in the leading state-of-the-art products today, the most aggressive design rules that companies are running in production are around a 60-micron, pad pitch. There is a nuance that often gets lost. If we were to conjure up and deliver a 20- or 40-micron pad pitch bonder tomorrow, no one could use it because there is no silicon designed for that production system.

So when we demonstrate our ATX1--which is our next-generation bonder with 35-micron pad pitch capabilities--it's not available for production today but it is intended to give customers the confidence to move down to that pitch size. As customers scale down their feature sizes, they can also scale their design rules down and start designing parts for production in 2001 that are going to be 35-micron pad pitch capable.

The question is, where do you go beyond 35 microns? We now believe that 35 is simply a matter of some hard work and is absolutely a doable process. Where we go beyond 35 has less to do with the machinery than it does with the wire. The wire must continually get thinner. The problem with making the wire thinner is that as you shrink the chip, the wires get longer. Either the substrate has to change to bring the wires back down in length or something has to change in the molding process because these very thin wires don't mold well.

As we look at it today, we have more technological headroom in the bonder than in the upstream and downstream processes. So, as to what is the pad pitch limit in wire bonding we will not give as hard of an answer as we might normally give. We don't know yet what can be done upstream and downstream on the assembly line. But wire bonding will certainly scale to 35 micron, at least.

QUESTION: What kind of investment is being made by K&S to address challenges in the semiconductor technology roadmap?

KULICKE: One challenge for us on the roadmap--on the non-wire bond side--is no-lead bump structures on wafers for environment issues. We are in alpha test now with no-lead wafer bumping. And in the 300-mm conversion, there is an initiative around wafer-level chip-scale packages, which we continue to invest in.

The big issue now is the substrate side. As we look forward, we probably think there is more leverage available for the industry in substrates rather than equipment, bumps, or other process issues. Substrate R&D is an expensive way to go. They are very expensive programs and factories, compared to the traditional bonder business.

I don't want anyone to misunderstand and think we are not putting a lot of money into wire bonding. We have been bringing out a new wire bonder roughly every 15 months. Those wire bonders have been in the neighborhood of 15%-to-20% more productive than their predecessors. These wire bonders have been reducing pad pitch in the neighborhood of 10 microns per successive generation. We don't see that letting up. The S and PPS are successors to the 8028. Sometime next year, we will bring out a machine that is code-named "ATX1"--the prototype is in the Semicon West booth--and our engineers are scratching their heads on the "ATX2."

We see no let up on the wire bonder side as well.

Wire bonders will continue to be the mainstream technology. The absolute number of devices that are wire bonded will continue to grow dramatically for the foreseeable future even though they will lose percentage share to flip-chip scale packages. It is a relatively balanced investment portfolio at K&S.

QUESTION: What do you think of system-on-a-chip vs. packaging approaches?

KULICKE: I think "system on a chip" was over-hyped to begin with. It depend upon what you mean by "system-on-a-chip." If you are going to start to dramatically mix process technologies, there are significant cost disadvantages associated with system-on-a-chip. System-on-a-package is one way around that.

Stacked chips, which is something that FCT Flip Chip Technologies joint venture with Delphi Delco Electronics Systems has done with redistribution structures and bump structures to get a "poor man's" system-on-a-chip by taking different chips built with different process technologies and mounting them together in one package. Ultimately the best leverage comes down to integration on silicon. If you can integrate on silicon in a standard CMOS process, then this system-on-a-chip becomes attractive. But when you have to diverge from that--mixing analog or memory process steps which are just different enough--some of the advantages for system-on-chip falls away. I think it SoC is more hype.

There are more two and three-chip packages out there than people realize. A not insignificant number of BGAs have more than one piece of silicon in them.

Today, wire bonding is probably 95% of the commercial chip volume. There is probably a two-to-three times cost penalty associated with flip-chip technologies. That cost penalty is almost exclusively in the substrate, and that's one of the things being addressed by Jack Belani, president of K&S's X-LAM Technologies subsidiary, which is pursuing proprietary multi-layer, thin-film organic substrates. So long as that cost penalty remains, flip-chip will only be used for high performance or small form-factor reasons. That cost penalty does come down as I/O count goes up, but it does not come down dramatically... So the issue becomes, how far will wire bonding scale in terms of electrical performance and footprint on a board?

Wire bonding will get better, but some of the improvements in wire bonded packages will also come from more expensive substrates. So the leverage or the "hinge" factor in all of this is the substrate.

At this point, there is surprisingly little being invested in substrates outside of K&S. Most of the substrate suppliers come from a PC-board technology, and they are still trying to get their arms around the micro-via, which will only solve the problem for a limited time.

QUESTION: In wafer-processing tools, suppliers beginning to tie machines to closed-loop control systems. What are you doing in terms of diagnostics and closed-loop control in assembly and packaging equipment?

KULICKE: The idea of building diagnostics feedback loops in the machine is something we have looked at in the past and we have limited diagnostics in some of the machines today. It is certainly possible to push that technology forward, and I think it will happen, although it is not a mainstream effort for anyone today.

The wire-bonding process is pretty robust with detect rates on a per-wire-basis in single parts per million. It is not a big priority for most companies.

QUESTION: With wires getting thinner, are you developing anything new in this area?

KULICKE: We are a significant supplier of bonding wire. We are one of the companies pushing development of very-high tensile-strength, gold wire so that the diameter can be reduced. There is also a significant cost reduction associated with diameter reduction.

Historically, the industry has run what's known as "4-nines" gold, which is 99.99% pure--24 karat is only 97%. This is very-high-quality gold wire. Then, we must introduce controlled impurities into the wire that impacts the mechanical strength. We have some "2-nines" gold that is very high strength.

QUESTION: What will be the cost difference between wire bonding vs. flip chip in the future?

KULICKE: We would never forecast flip-chip as saving cost. I don't think that is realistic. There is a performance advantage. There are advantages at the system level . . . from flip-chip technology. It is a tradeoff to make your computers go that much faster or to make your cell phones that much smaller vs. the higher package costs. I don't think that flip-chip itself would be a cost reducer.

This issue of new assembly technology vs. existing chip packages brings you to back into one of these funny conundrums in our business. If you are a merchant semiconductor company, packaging adds no value. It is a necessary "evil" to get your silicon to market. You really don't care very much about the package. And if you could get away with it, you'd stick all of your chips in very big DIPs because they are nice and easy to make.

But the packaging issues accrue almost entirely to the system-level producer. Even though system companies do not do the packaging, they are the beneficiaries of it-whether it is because boards run at higher clock rates, or boxes are smaller and lighter, or they consume less electricity.

You have this funny dynamics where the IC companies don't care very much about new packaging technologies, but their customers are driving them to it. Their customers are driving them to higher-cost packages, which make the ICs more valuable in the systems, but no one want to pay more for it.

QUESTION: How serious are chip companies in flip-chip investments?

KULICKE: A wafer bumping line is about a $25 million capital investment alone. In the backend, that's a big amount of money. But it is chump change in the wafer fab. These guys licensees would not spend the money if they were not serious.

The Flip Chip Technologies venture has licensed its wafer bumping process to U.S.-based Amkor Technology Inc. and Taiwan's Siliconware Precision Industries Co. According to K&S officials, Siliconware is now equipping its facility in Taiwan, while Amkor is finishing up initial personnel training and in the midst of equipment selection.

QUESTION: Do you think there be a consolidation of test and assembly equipment suppliers?

KULICKE: There has been no movement yet between the test and assembly segments of suppliers. There is some movement in the test segment to bridge traditional tester problems with socket and device handling problems. Teradyne, in particular, has done some work there. But I think it is reasonable to forecast a convergence of suppliers in automatic test equipment and assembly tools.

We are certainly working on packaging technologies that strain testability-not so much testability inside the tester but at the socket or probe-card area. We have to start to take into account that class of problems. And this means it would be reasonable to forecast some convergence of suppliers down the road.

QUESTION: Will today's strong business and growth conditions continue for the semiconductor industry?

KULICKE: First, this cycle has already lasted longer than most upturns. So, we are essentially in uncharted territory. But this is sort of a "John Joseph question," who has said the party is about over Salomon Smith Barney's chip analyst who in early July made a controversial industry forecast and downgraded chip stocks. We don't see it that way.

We are probably about as cynical as anyone in this business in that we think there will be another downturn. The nature of that downturn will most likely be that our customers will invest in excess capacity, and in an effort to keep that capacity busy, they will cut their chip prices. Their profit margins will go to hell and they will cut back in capital investments. That kind of fundamental semiconductor cycle will repeat itself.

The issue is when. How quickly can our customers inflict this on the industry? The good news, in our opinion, is that it will not happen as soon as some people think.

For a number of reasons, wafer fab capacity is not coming on stream quickly and it will not come on stream as quickly as some of the optimists believe. One very central reason for that is simply that not enough stepper lens sets were started 18 months ago. The cycle time to build a stepper, including building the lenses is in the neighborhood of two years... That puts a natural throttle on the business.

Secondly, a significant amount of incremental capacity is coming in as greenfield 300-mm wafer fabs, and they are going to be a bear to bring up. That also mitigates it the rapid expansion of capacity a bit.

Thirdly, a lot of incremental capacity has come through device shrinks in the last two or three years. A lot of those fabs are just shrunk out. They have reached the point to where they just have to start over again. You must replace so much of the equipment that you will have virtually rebuilt an entire wafer fab in the old building.

We feel quiet comfortable in saying that 2001 will be another significant up year--perhaps not as strong as 2000 was--but it will be a good year. And now we are worrying about 2002, but even there the wafer fab guys probably cannot install that equipment as quickly.

That's our answer to John Joseph He then gives out a long, loud raspberry or Bronx cheer..

QUESTION: While you say 300-mm will be slow to ramp, others experts at Semicon West predicted 300-mm will be easier to bring up. For one thing, many believe the industry has had a lot of time, and customers are getting bridge tools. Won't that help 300-mm ramp into volume sooner?

KULICKE: It seems to me that a bridge tool is a way to build a 300-mm fab and run it as a 200-mm facility until someone else figures out how to solve the problems. It sounds to me like a slow ramp. It gives you all of the bragging rights of 300-mm, but the production yields of 200-mm.

The industry is now looking at taking on three simultaneous challenges: 150-nm 0.15-micron processes, 300-mm wafers, and copper interconnect. And low-k is a fourth. That's a lot to swallow. I'll say this, however, the first company that figures it out will have a significant edge for a while. But I don't think these are trivial problems.

In some ways, it will be easier to make the switch from 200- to 300-mm in a memory application vs. a logic application referring to Infineon's early achievement in high yields on 300-mm with 64- and 256-megabit DRAMs at its joint-venture fab with Motorola Inc. in Dresden, Germany. I would be careful in extrapolating from one to the other. There are fewer metal layers in DRAM than in high-end logic. It is just easier to build DRAMs on 300-mm wafers.

QUESTION: Earlier this year, some analysts warned that lead-free initiatives in Japan and Europe could be a problem for the electronics industry. How do you see this kind of thing impacting chip assembly? Will the industry find reliable alternatives to solder and lead-based materials for interconnects?

KULICKE: We are seeing significant pressures for lead-free solutions in flip-chip. We have lead-free parts in evaluation now. We don't see that it is particularly a big deal going forward, however. It is an engineering issue and there is no "invention" necessary.