TSMC proposal for 0.10-micron standards won't initially include foundry competitors

TSMC proposal for 0.10-micron standards won't initially include foundry competitors
SAN JOSE -- During press conferences in London and Munich this week, Taiwan Semiconductor Manufacturing Co. Ltd. caused a bit of a stir in the chip industry by announcing efforts to set a single, "open" standard for 0.10-micron process specifications. With fewer IC makers able to keep up in next-generation processes, TSMC managers said it's time to set standards at the 0.10-micron technology node and help speed products to the market in the next several years (see Sept. 17 story).

More details about those efforts will be released by TSMC before the end of this year, but a U.S.-based spokesman told SBN that these "open" specifications will probably not be open to silicon foundry competitors. Instead, TSMC's effort is focused on reaching agreements with semiconductor companies that own and operate wafer fabs but also use third-party foundry services.

"We are getting agreements in place with IDMs integrated device manufacturers, and we have multiple agreements already in place," said the TSMC spokesman. "We have LSI Logic, National Semiconductor, and NEC--they have all indicated that they want to work with us to this end goal, but we have other discussions underway as well."

When news of TSMC's efforts first hit this week, some foundry competitors initially embraced the concept of specification standardization at the 0.10-micron (100-nm) technology node. In fact, Singapore-based Chartered Semiconductor Manufacturing Pte. Ltd.--the world's third largest pure-play silicon foundry--said it had floated a similar concept for process standards in recent years, but the idea never got off the ground.

Like TSMC, managers at Chartered Semiconductor said they see huge benefits for the chip industry from a common set of open definitions in electrical and interconnect specifications. Common industry specifications for baseline 0.10-micron CMOS digital processes could help reduce costs in design libraries and reusable intellectual property (IP) cores from third-party providers, said John Martin, chief technology officer at Chartered.

"It would promise significant advantages for the industry in at least the core logic area to have design rules and electrical parameters aligned," Martin said in an interview this week after TSMC's disclosure. The chief technology officer said "tremendous variations still exist in processes at individual companies" despite the industry's decade-old efforts to use an international technology roadmap sponsored by the Semiconductor Industry Association. The problem with the SIA roadmaps has been the lack of details about key performance and electrical parameters resulting from various process targets, he told SBN.

Good time to start

"The 0.10-micron node probably has sufficient lead time for an effort to define initial specifications," Martin suggested. "It will be just a little under 18 months before each of the three major foundries expect to have 0.10-micron technology in pilot production. We probably have enough time to bring that to together."

And perhaps the efforts to create standard specifications will be as important as the end results at the 0.10-micron node because the chip industry faces much bigger technology and design hurdles in the subsequent process generation with a target of 0.08 or 0.07 micron (80-to-70 nm). "There are more evolutionary changes going from 130-nm to 100-nm compared to the next node at 80-to-70 nm," Martin noted. "We are probably looking at the need for completely new materials for high-k electrics in the transistor and much different low-k materials for the interconnect.

"The implementations could end up being quiet different, but it we all align the targeted electrical specs, that would greatly narrow the variations for IC design considerably," he added.

Both Chartered and TSMC see a similar benefit from common process specification in the next-generation technology, but it currently appears these foundry competitors--and probably others--are in disagreement about the way to set industry "open" specs.

"We are discussing a variety of alternatives to how the specs will be defined and managed," said the TSMC spokesman. Initially, the Taiwan foundry giant is focusing its efforts on IDM customers but "whether or not this becomes something larger is still under discussion," said the spokesman. "But I cannot imagine why we'd include other foundries. We are in a technology leadership position already and all we would be doing is helping others close that gap."

'Open' vs. 'semi-open'

Chartered managers said the only way an industry standard could be successfully set for process specifications would be through an independent third-party organization--such as the Fabless Semiconductor Association, the IEEE, or some other trade group.

"We're not sure what they TSMC are talking about. It seems to be some kind of a 'trial balloon,'" said Michael Buehler-Garcia, vice president of marketing and worldwide electronic design automation manager for Chartered.

"If this is truly an open standard, then it has to be open for participation by competitors," said the EDA manager, who is based in Milpitas, Calif. "That's the No.1 requirement. Then No.2 would be whether or not we are allowed to participate from the beginning and not have something handed to us after a specification is completed. And No.3 would be the question: who owns the results of the 'open' collaboration? This must be placed in the hands of a third party so that derivatives and donations in the future continue and the next node isn't close."

Chartered would be interested in starting with open standards for design rules dealing with the interconnects, Buehler-Garcia said. These would help designers and foundries deal with electrical parameters and other issues related to speed and performance.

Same results but different fabs

Both TSMC and Chartered believe common specifications on 0.10-micron processes do not have to define tool sets or materials in wafer fabs. Instead, these foundries believe specs could be defined for the output in a fab.

"We have a lot of experience in delivering electrically equivalent processes to IDMs," said Chartered's Buehler-Garcia. We know what the target is and we use potentially different equipment in the fab and different materials, but we can hit the same target... Going forward, product differentiation will be based on the market that's being targeted and not the baseline process."

TSMC agrees that process specifications are playing less of a role in which products are successful and managers maintain that it is time to create common specifications to help speed IC development--especially in the system-on-chip era. And the Hsinchu, Taiwan-based foundry hopes to settle on specifications that will match up with IDM processes so that products can be transferred to different fabs depending upon volume production requirements.

"Over the course of the last decade or so, the semiconductor industry generally has shifted toward a foundry-centric business model," said Genda Hu, vice president of corporate marketing at TSMC, who announced the 0.10-micron standard efforts at a London process conference. "Today, IP and library developers, EDA companies and others tend to verify their products on TSMC silicon before going anywhere else. Similarly, the majority of fabless companies and IDM companies worldwide have both prototyping and volume manufacturing relationships with TSMC." He indicated that it makes sense to standardize on TSMC's platform.

In San Jose, the U.S. spokesman said more details about the standard specifications will be released by the end of this year. "At a higher level you can get the same design rules with identical electrical characterization from similar processes, but this does not mean the equipment set in our fabs and IDMs will be the same," he said. "Just the output has to be identical. That's what we're shooting for in this effort."