Mentor launches effort to redefine FPGA synthesis in next 18 months

WILSONVILLE, Ore.--Mentor Graphics Corp. here today announced it was stepping up its overall focus in design synthesis software for field programmable gate arrays (PFGAs) and pooling resources into a new FPGA Synthesis business unit to execute a new technology roadmap over the next 18 months.

"The advent of system-on-chip (SoC) designs on programmable logic platforms requires EDA vendors to adapt their tool offerings to deal with unprecedented technical challenges, including massive frequency increases and exponential gate count growth," said Walden (Wally) C. Rhines, chairman of the board and chief executive officer at Mentor. "In the programmable logic market, technology and chip complexity are moving faster than anticipated. In order to remain ahead of the curve, Mentor Graphics has turned significant corporate resources to this market space," he added.

To speed up its developments in the segment, the Wilsonville design automation supplier said it has assembled synthesis experts into a R&D team to advance the state of FPGA synthesis. Developers and scientists will address a range of hardware and software systems to address all areas of synthesis, including register transfer level (RTL), physical and behavioral design technologies, according to Mentor.

Named "Project Atlanta," the technology roadmap calls for new synthesis capabilities to be delivered in three phases over the next 18-months: phase I (heuristic synthesis); phase II (physical synthesis); and phase III (high-level synthesis). Mentor said the first phase of Project Atlanta will be released into a beta program in the fourth quarter of 2001.

In the first phase of the project, Mentor said it will focus on a new approach to FPGA synthesis, known as "heuristic synthesis." This concept incorporates years of design knowledge into the synthesis tool enabling it to focus on larger building blocks in the design, such as central processing units (CPUs), ROMs, RAM, content addressable memories (CAMs), and other functions to build very fast and efficient structures.

In phase two, Mentor plans to deliver what is says will be the industry's only "true physical optimization solution" for FPGA-based designs. The company plans to leverage technology from its portfolio of ASIC timing closure tools, called TeraPlace, in the second phase of the project to merge physical information and data with synthesis algorithms. Mentor said FPGA designers will be able to improve design performance by replacing inaccurate wire load models with data that properly accounts for interconnect delays.

In the third phase of the Atlanta project, Mentor said it will make available synthesis software that enables engineers to design at a higher level of abstraction, allowing for rapid design exploration and implementation.