Chartered rolls out two 0.13-micron copper processes with two low-k approaches

Chartered rolls out two 0.13-micron copper processes with two low-k approaches
SINGAPORE -- Chartered Semiconductor Manufacturing Pte. Ltd. today announced delivery of its first 0.13-micron all-copper interconnect ICs to a silicon foundry customer, Integrated Silicon Solution Inc. (ISSI), and the Singapore company said it has begun fabricating devices with a next-generation copper processes using a low-k dielectric technology jointly developed with Agere Systems Inc.

The low-k process uses chemical vapor deposition (CVD) technology from Novellus Systems Inc. for layering of Novellus' Coral thin-film dielectric material for insulators between copper metal. Novellus' tools are also used for copper seed and plating of metal in the new 0.13-micron interconnect technology, said John Martin, chief technology officer at Chartered Semiconductor. A dielectric constant of 2.7-to-2.8 is achieved in the jointly developed process.

Chartered's low-k technology is a result of an R&D alliance with Agere (formerly Lucent Microelectronics). Last summer, the two companies announced a $700 million R&D partnership to help accelerate the use of copper, low-k dielectrics and other processes for communications ICs (see Aug. 9 story).

"The introduction of this low-k 0.13-micron copper process is right on schedule with the accelerated development plans," Martin said.

The CVD-based low-k copper process is now scheduled to be introduced into production as early as the first quarter of 2002, initially using 200-mm (8-inch) wafers. It will migrate to 300-mm (12-inch) wafers when customer capacity demand requires larger substrates, Martin said.

Meanwhile, Chartered is also pushing ahead with its current implementation of all-copper processing at the 0.13-micron node, using fluorinated silicate glass (FSG), after delivering the first devices to ISSI of Santa Clara, Calif. Chartered shipped high-performance SRAM fabricated with the 0.13-micron technology to ISSI last month. Volume production of ISSI SRAMs is expected to ramp up in the second half of this year, said Chartered.

"The process results in an SRAM cell size as small as 1.97 micron squared, which we believe is one of the smallest demonstrated at the 0.13-micron technology node," Martin told SBN in an interview.

Chartered has taken a dual-track approach to 0.13-micron process development with one team focused on FGS for low-k dielectrics and the other working jointly with Agere using new thin-film materials for even lower dielectric constant levels. The FSG dielectric process is currently done with 248-nm lithography in critical dimensions, using phase-shifting photomasks and optical proximity correction (OPC).

The CVD-based copper technology jointly developed with Agere, uses 193-nm scanners for the most critical dimensions. Martin did not say which tool vendor was being used for those steps. The develop team fabricated a five-layer metal SRAM using the new 0.13-micron copper/low-k process. Up to eight layers of metal are possible in the low-k process, said Chartered.

"We believe the demand we are seeing for prototypes at 0.13-micron and copper is quiet strong, and I anticipate that mainstream activities for 0.13-micron will certainly occur in 2002," he said.

The CVD Coral processes for dielectrics enables a 20% reduction in interconnect delays compared to FSG materials, which have a k value in the 3.6 range.

--J. Robert Lineback reporting from the U.S.