Intel technologist cites power as biggest issue

Intel technologist cites power as biggest issue
SAN FRANCISCO — Moore's Law brings more than increases in the number of transistors per chip; it also brings dramatic increases in power consumption and power density. If current trends continue, you would have a device with 425 million transistors in 2005 and a processor with 1.8 billion transistors by 2010, said Pat Gelsinger, Intel's vice president and chief technology officer. You'd also have a heat generator with the intensity of a nuclear reactor, he said.

Indeed, power consumption will be the key concern for microprocessor technology, said Gelsinger during the morning plenary sessions at the International Solid State Circuits Conference (ISSCC) here. Despite the trend to scale processes, increase clock CPU clock frequencies, and attempt to conserve power by lowering operating voltages, large-scale integrators like Intel are running out of head room when it comes to power consumption.

Even using 0.1-micron technology, Gelsinger envisions a 425-million-transistor die, 40 mm per side, which, clocked at 30 GHz, would dissipate 3,000 to 5,000 watts. In terms of power density, its heat would be close to that of a rocket nozzle, Gelsinger said. Conventional methods of using lead frames and specialized heat sinks will not cope with the power density. "Going forward, I don't think we know how to cool a 5000-watt processor," Gelsinger said. "We can't keep building these things with ever-increasing power budgets," he lamented.

Efforts to hold down die size with scaled CMOS geometries may still result in prohibitive power consumption. The current-generation Pentium, produced in 0.125-micron CMOS, dissipates about 66 watts. The same device in a 0.1-micron process — clocked at GHz rates — would dissipate (say) 200 watts. With a 1-V supply, the current consumption would be on the order of 200 amps. "We cannot continue the same trend," Gelsinger concluded. "Are you depressed yet?"

While he avoided sounding like Pollyanna, Gelsinger pointed to architectural techniques that offered some optimism on the power consumption technique. The techniques encouraged the processor to higher levels of efficiency by forcing it to do more work when it was on; and throttling it down when it wasn't working. These techniques include multithreading, in which a single processor performs multiple tasks. It was more than parallel execution (like VLIW), but rather the ability of a scalar machine to track multiple threads. This would require a 5 to 10 percent increase in in-chip logic but would provide a 20 to 40 percent increase in performance, Gelsinger speculated. It would also save memory bandwidth and lower the processing overhead associated with a cache miss.

What Gelsinger calls a "wider/deeper machine" (a wider word width or a deeper pipeline) would not provide the desired power efficiencies. But he did call for more aggressive power throttling. If they are not doing something in the signal chain, "turn transistors off," Gelsinger said, a note reminiscent of current California energy conservation efforts.