IEDM late paper: IBM shows how to stack for 3D circuitry

IEDM late paper: IBM shows how to stack for 3D circuitry
LONDON -- The possibility of creating three-dimensional circuit blocks is the topic of a late paper from IBM researchers at this year's International Electron Device Meeting (IEDM) to be held December 8 to 11 in San Francisco.

A team led by Kathryn Guarini from IBM's T.J. Watson Research Center in Yorktown Heights, New York, has mated together two circuits from atop separate silicon-on-insulator wafers using a "glass-handle" transfer method and have done so, they claim, without significantly degrading the electrical characteristics of the circuits.

Three-dimensional circuits hold promise for the industry for a number of reasons.

The primary reason is density of integration, especially if the 3D assembly process can be repeated to build up multiple layers. Along with integration comes improved performance and lower power consumption because, for a given number of transistors, a 3D arrangement should yield shorter average interconnect distances and delays than a 2D arrangement.

That physical arrangement may be significant when it comes to supporting modern computing architectures. With 2D circuits it is already becoming difficult to provide enough input and output "bandwidth" to keep up with a high-speed processor or a multi-processor array.

Other benefits for 3D integration listed in the IBM late paper include lower noise coupling, because of shorter parallel runs of interconnect, and the possibility that in the future heterogenous materials could be stacked, allowing say silicon-germanium in one layer to provide RF circuits, while silicon CMOS provides digital logic circuits in another layer.

At IEDM the IBM researchers will describe how they began with a silicon-on-insulator wafer, with a thin layer of active silicon as its top surface. In this layer they fabricated conventional transistors and simple circuits in 130-nanometer process technology. The glass "handle" is attached to the top of the wafer, above the circuitry. From the underside the wafer is then etched and ground back to the buried oxide layer.

Using the top-side "glass handle" the formerly buried oxide layer, now the exposed bottom-side, is bonded to a SOI wafer with complementary active circuitry. To complete the process the glass handle is removed and necessary vias inserted to link the 3D circuit together. IBM included a number of circuits composed of 55-nm CMOS inverters and a 65-nm ring oscillator circuit on the top layer demonstrated an 11.8-picosecond stage delay, according to the paper.

The 'glass-handle' transfer method is, in itself, not novel. Indeed it is one of the methods by which virgin SOI wafers are made. The contribution of Guarini and her team is to demonstrate the process of glass attach, removal and wafer-to-wafer bonding without degrading the performance of the circuits being transferred. The key is to perform the operation at low temperature and with minimal mechanical strain, the authors state.

The IBM method uses polymeric adhesive bonding to attach the glass handle, rather than oxide-to-oxide thermal bonding, and laser ablation and adhesive striping for glass release.

The technique for aligned bonding of the buried oxide layer of the transferred circuit with a top oxide layer of a receptor circuit is not explicitly discussed in the IBM paper, but the paper does state that for both n- and p-type 65-nm FETs there were in only small percentage variations in on-current and negligible changes in linear threshold voltage.

However, one problem with 3D circuit stacking that the IBM paper does not seek to address is how to get the heat out. While the IBM research is based on measurements of simple circuits the 3D stacking technique would clearly come into its own if circuits of contemporary complexity could be stacked two, three, or more layers deep. However, some single-layer 2D circuits are already providing thermal challenges and multi-layer stacking to form a glass block would exacerbate this.

It may be that any commercialisation of IBM's 3D technique would have to be accompanied by physical channels for fluid flow cooling or copper pathways for heat to flow out of the stack.