LSI Logic platform said to speed custom chip design

LSI Logic platform said to speed custom chip design
NEW YORK — Hoping to take some of the cost and pain out of ASIC design, LSI Logic Corp. will unveil a new silicon platform and design software on Wednesday (Sept. 4) that lets designers churn out custom chips at a faster clip.

The RapidChip ASIC platform promises to deliver most of the performance of a standard cell design while hiding much of the complexity within pre-diffused intellectual property (IP) "slices" that have been fabricated prior to final customization, LSI Logic said. Both the silicon platform and tools are being tailored to serve specific vertical markets, beginning with communications and networking.

Customers can add one million to eight million of their own logic gates to a design and configure embedded memory blocks to fit their needs. The final design is then handed over to LSI Logic for final physical layout and metal mask customization. LSI Logic says it can turn around a prototype within three weeks of receiving a netlist. All told, the entire design cycle can be completed in six months, or about half the time required for a standard cell ASIC, according to the company.

Richard Marz, executive vice president of communications and ASIC technology at LSI Logic (Milpitas, Calif.), said a RapidChip design will provide "80 percent of the performance of an ASIC at 10 to 15 percent the cost of an FPGA." Non-recurring engineering (NRE) costs would be in the "hundreds of thousands of dollars," which would make it economical for volumes of just a "couple thousand units," he said.

The RapidChip platform will tie in a design methodology and tools intended to help designers get through timing closure and verification on the first pass. By next year, LSI Logic plans to streamline the methodology by offering a "shrink-wrapped" tool set that mimics an FPGA tool flows.

"One of the objectives is to make the flow very attractive to people who have become familiar with FPGA-like flows in terms of simplicity and the predictability of results," said Chris Hamlin, chief technology officer at LSI Logic.

More control, more customers

ASIC designers that opt for RapidChip will have to take more responsibility for their design, particularly at the back end. "More ASIC customers want to have more and more control over their physical placement and physical design," Marz said. "The key to opening the funnel is to have it where the customer does virtually all the work."

By reducing NRE costs, compressing design cycles and streamlining the design flow, Marz said LSI Logic has an opportunity to see its customer base grow from the hundreds to the thousands. RapidChip designs will be available on the company's 0.18- and 0.11-micron design rules and designers will have access to the company's IP libraries for both technology nodes.

LSI Logic has been working with early customers on the new platform and expects to ship its first RapidChip products by the first quarter of 2003.