Chip makers throttle performance to meet price targets

Chip makers throttle performance to meet price targets
SAN MATEO, Calif. — Just as U.S. automakers were forced to build fewer gas guzzlers when oil prices were on the rise in the 1970s, the chip industry is coming to grips with the reality that raw speed and performance just don't sell like they used to.

Explosive growth in the late 1990s fueled an insatiable appetite for cutting-edge designs, but today, designers from many corners of the IC community are stepping on the brakes. Higher clocks don't always fetch a premium as they once did, and in some cases are being ratcheted down. Circuitry designed to give performance an extra kick is being ripped out. Ambitious chip designs intended to process packets at the fastest line speeds are being shelved.

Why has an industry famous for predicting an ever-rising need for more bandwidth suddenly turned meek? The short answer is changing economics. Semiconductor prices — measured per unit, rather than the more ambiguous "system cost" that is often cited — have come to top OEMs' agendas as many of them struggle to keep their heads above water. And since price is often at odds with device performance, chip companies sometimes find they have to scale back their designs to meet stingier purchase-order requests and shrinking product-development budgets.

Some companies will go so far as to cripple a chip's performance if it means it will sell in decent volumes. Consider SandCraft Inc., a maker of MIPS-based microprocessors. Last February, the Santa Clara, Calif., company rolled out a CPU with a relatively large (512-kbyte) secondary cache and a tertiary cache tag for external SRAM. The point of adding the large memory block was to avoid performance degradation in switching gear that incorporates firewalls or heavy quality-of-service features.

Last week, SandCraft announced a second version of the processor based on the same design that cuts the cache size from 75 percent of the die to less than one-third of the chip area. Though the latest version still runs at the same 600 MHz as the earlier CPU, it isn't expected to turn many heads when it comes to handling networking services. But thanks to the smaller die size and higher wafer yields, the company was able to lower its price tag to $50, less than half the cost of the initial cache-laden part.

The reason SandCraft made the change, said chief executive officer Paul Vroomen, was to woo price-conscious customers looking to extend the life of their existing networking gear. The networking industry has shrunk to the size it was 18 months ago, and more OEMs are axing some of their most ambitious projects, said Vroomen.

"We're seeing projects cut back across the board," he said. "For their own survival, systems companies are trying to minimize cost by extending the lifetime of existing systems."

FPGA vendor Xilinx Inc. is another company that recently hobbled performance to lower prices. Just months after rolling out its most recent Virtex-II FPGA with embedded PowerPC processors, the San Jose, Calif. company laid out another product offering at new density levels and with embedded processors that run at 266 MHz instead of the 300 MHz of the earlier devices. Most striking was the cost difference: The lower-speed versions are one-third to a little more than half the price of the parts with the 300-MHz PowerPCs. Xilinx said it was able to make the price cut because of its anticipated move to larger, 300-mm wafers and the higher wafer yields that come with the 266-MHz parts.

The company decided on the changes after talking to FPGA designers at a recent sales conference where it promoted the new architecture. "They kept saying, 'If we don't need that much bandwidth, we don't really want to pay for it either,' " said Steve Sharp, senior manager of silicon solutions at Xilinx.

Network processor companies are also finding it hard to pitch higher-performance devices to telecom OEMs struggling with a spending freeze on new telecommunications equipment. Many of these chip makers have put on hold plans to field devices destined for 10-Gbit/second links, and are instead seeking ways to upgrade their existing architectures for OC-48 (2.5-Gbit/s) speeds. Among them are Access Networks, Azanda, Silicon Access Networks, Vitesse and ZettaCom.

Stall in design starts

Custom chip designs, which often integrate a system company's most prized intellectual property, haven't been immune from the budget ax either. ASIC design starts have been falling, and those now going through the pipeline are often not designed for blazing logic speed.

Wilfred Corrigan, chairman and chief executive officer of LSI Logic Corp., said IC designers and their customers are increasingly worried about how they will fare in the next six months. Companies often used to employ two design teams that worked in parallel to meet an aggressive product road map, but in the uncertain business climate that practice is being abandoned, he said.

"I don't think these last two years have been a time when people are doing interesting things," Corrigan said. "Instead of people gambling with the long ball, customers have become cautious in their design cycles. People have been less bold about pushing out new products."

Part of the caution has to do with the risks involved in designing ICs. There's a general trend among ASIC designers to become more involved in physical design, especially at the high end. Companies that can pay for the engineers, tools and a design methodology can usually maneuver their way through these back-end design pitfalls. Those that can't are encountering more snafus at the end of the design cycle, often to the detriment of performance.

ASIC vendors like LSI Logic say they need better visibility into customer designs earlier in the cycle if the final design is to meet specifications. "We're not talking about just RTL register-transfer level handoff, but how good was the RTL," said Richard Marz, executive vice president of communications and ASIC technology at LSI Logic (Milpitas, Calif.). "And all RTL is not created equal."

Further, many chip executives say the industry has failed to come to grips with the problems at the 130-nanometer (0.13-micron) node, even as some manufacturers are starting to tout their forthcoming 90-nm process technologies. The difficulties include meeting timing closure, skyrocketing mask costs and problems integrating new materials such as low-k dielectrics and copper interconnect. As a result, designers are having to wait longer for the process technology to mature before they can exploit its performance advantages.

Not 'God's gift' yet

"The 0.13-micron process technology was supposed to be God's gift to mankind, but it still hasn't turned out that way," said John East, president and chief executive officer of FPGA vendor Actel Corp. (Sunnyvale, Calif.).

Others say it is creating a rift between the haves and the have-nots: "0.13 micron is being driven by a small group of people," said Stephen McMinn, president and CEO of ASIC vendor Chip Express. "The FPGA guys have to do it and then there are the high-volume designs, say if you're going to do a Playstation chip. Most are just afraid to go to 0.13 micron and are going to stay at 0.18 micron unless they absolutely have to make the change."

One frightful fact about leading-edge chip design is the escalating cost of the masks, which are more than $700,000 at the 0.13-micron level and will top $1 million at the 90-nm node — potentially enough to cripple a company's financial standing if something goes awry.

"Customers don't have the time to get it wrong and they can't afford another spin," said Cindy Genther, ASIC marketing manager at Agere Systems Inc. "If they take a second spin or shift too soon to the next-generation technology and the markets aren't ready, they could wipe out their entire company."

But the industry has faced down seemingly intractable problems before. "I remember when two and three levels of metal were the standard and the thought of adding a fourth level of metal was thought to be inconceivable. We're up to 10 levels now," Genther said.

Still, the same market forces that ravaged their customers are making it harder for chip companies to plow through these design and process issues as they occur. In the short term, at least, that could mean the price/performance balancing act will tip in favor of lowering development and production costs to meet more-aggressive price targets.

Changing that scenario will likely depend on how soon the industry makes a meaningful turnaround. When the chip business is growing at a fast clip, designers and manufacturers have the means to work through some of the toughest issues. But until chip companies and their customers have a better sense of the business outlook beyond the next six months, minimizing risk will remain the credo.

"If you're growing 30 percent a year you can overwhelm these things with more money," LSI Logic's Corrigan said. "The fundamental issue is that the industry needs to grow again."