Designers report on multi-million gate ASICs

Designers report on multi-million gate ASICs
NEW ORLEANS -- A Design Automation Conference special session here Wednesday (6/12) posed a question of very real importance to a growing number of design teams: is a 10-million gate ASIC feasible? The easy answer was affirmative, as all three of the papers in the session were given by engineers who had recently managed designs of at least that size. But the yes answer came with serious qualifications.

The session began with one of the densest commercial chips produced to date. Chris Malachowski, vice president of engineering at Nvidia, described the GeForce 4, the latest in that company's line of high-end graphics chips. At 63 million transistors and a core clock frequency of 300 MHz, the chip is ambitious by any measure. But considering that 78 per cent of the die is logic places the undertaking in perspective.

Compensating somewhat for the sheer size of the design, the chip is based on an existing architecture. Yet Malachowski said that nearly 50 per cent of the RTL had been modified from the previous family member, so the complexity was not reduced that much by reuse.

Malachowski described a rigorous but relatively conventional design flow for the 150-nm chip, starting with intensive modeling of the design in C. The C code was then used as a reference model while the design was recoded in Verilog. Malachowski commented that there was no great simplification in the behavioral model: the design required 400K lines of C code, compared with 800K lines of Verilog.

Malachowski said that by their metrics the design had been a great success. First silicon had 19 reported functional problems, only seven of which required repair. All seven were corrected in the metal, allowing the team to meet its target of approximately 9 months to tape out and 100 days between tape-out and production ramp.

Experience was the key to solving problems, Malachowski said, illustrating his point with dramatic improvements in timing on some blocks since the previous chip. Yet he worried, he said, about whether the team was really good or just really lucky. "It's hard to judge when you are through with verification," Malachowski commented. "Even with great stuck-at coverage, the only proof is that the chip works in applications. And it's not the logic errors. Logic screw-ups cause a metal spin. Noise problems can be a lot worse to fix."

Aurangzeb Khan, group general manager at Simplex, added his vote to the "yes" side of the question. He described a series of analysis techniques, including advanced interconnect modeling and a design flow based on physical re-synthesis, detailed IR-drop analysis and crosstalk prevention, that has produced 23 tape-outs for the physical design service, all successful at first Silicon.

But in a cautionary "your results may vary," Khan detailed how Simplex builds techniques upon research, then constructs methodology on techniques, and finally builds commercial tools from maturing methodology, again emphasizing the irreplaceable role that personal experience plays in success.

The final vote came from Christian Berthet of ST Microelectronics, who described development of a GPRS feature phone chip. The design hinged on reuse of major existing cores, including an ST120 DSP core and an ARM core. Yet it still required 100K lines of C verification code, two different ASIC emulation environments - one from Aptix and one custom FPGA-based - and five man-years just to create the verification code.Berthet said that the design drew on not only existing large cores, but on ST's experience at every level from requirements definition to test design.

The three designs showed several common features. One was short duration, but with large design teams - typically from 40 to 70 engineers in implementation alone. The efforts were also greedy for capital. Malachowski estimated that Nvidia spent $160 million on tools and $40 million just on emulation systems for the project.

The full size of the expense emerged at the end of the session, however. Khan etimated that Simplex physical design services for a chip of this size would cost between $2 million and $5 million in non-recurring expense by tape-out.

Before that number could fully sink in, Malachowski related that in an informal estimate, he and another Nvidia executive worked out that the GeForce 4 had probably cost the company $100 million altogether.

That made the full answer to the question clear. Yes, a 10-million gate ASIC can be done successfully. But the front-end investment is staggering, and any attempt to save increases risk. At this point it is a club that only the heavily funded, with almost certainty of a massive market, can enter.