TSMC to offer 90-nm prototyping services in Q2 and SOI wafer option

TSMC to offer 90-nm prototyping services in Q2 and SOI wafer option
SAN JOSE -- During a technology symposium here today, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) outlined and disclosed accelerated targets for next-generation ICs fabricated with 90-nm (0.09-micron) process technology.

The world's largest silicon foundry said it now plans to start offering 90-nm prototyping services this quarter, and "risk production"--or early production--will begin with the CMOS technology in the third quarter of 2002.

TSMC also disclosed that it will enter the emerging silicon-on-insulator (SOI) foundry market, offering SOI wafers as an option to its new 90-nm process.

The foundry giant's 90-nm technology--which the company now calls "Nexsys"--will not only encompass an SOI option but it will also feature a wide range of process derivatives, ASIC libraries, and intellectual-property (IP) cores to enable next-generation chip designs. The 90-nm Nexsys process will be initially used on 200-mm wafers, but TSMC said it plans to use the technology for early production on 300-mm wafers in the first quarter of 2003.

"Nexsys is a technology that will enable SoCs system-on-a-chips," said Genda Hu, vice president of corporate marketing at TSMC, during a presentation at the company's "2002 Technology Symposium" in San Jose.

Last month, the Taiwan foundry giant claimed to be the world's first chip maker to demonstrate a functional IC based on 90-nm technology (see March 5 story). The Hsinchu, Taiwan-based company claims to have demonstrated a 4-megbit six-transistor SRAM test chip using 90-nm process ahead of even IBM, Intel, and other leading-edge semiconductor manufacturers. (Intel Corp. disclosed its 90-nm SRAM test chip one week after TSMC's announcement, and it also claimed it was ahead of other companies in producing prototypes, see March 12 story.)

A month ago, TSMC said it would produce chips at the 90-nm node during late-Q3 or early-Q4 of 2002. And the foundry company said it was joining forces with two leading European chip makers to help develop the future technologies--Philips Semiconductors and STMicroelectronics Inc.

During the technology conference here today, TSMC officials dropped hints that it is now attempting to accelerate availability of its initial 90-nm process in an effort to stay one step ahead of its foundry rivals as well as the top integrated device manufacturers (IDMs), including Intel.

And the Hsinchu-based company appears to have the ball rolling. At the symposium today, TSMC announced plans to offer its CyberShuttle multi-project wafer prototyping services on 200-mm (8-inch) substrates, beginning in the second quarter of this year--which is much faster than analysts originally expected.

The cost-sharing prototyping service will be offered on 300-mm multi-project wafers in November, said TSMC officials. Multi-project wafers pack a number of different chip designs on a single wafer to share the cost of photomasks, processing steps, and materials.

Starting in late-Q3, TSMC said it intends to move the 90-nm technology into "risk production." This stage of early production is for the early adopters of technology, which are often strategic foundry customers. The company's 90-nm technology will continue to ramp and move into volume production by year's end and well into 2003.

The company's first processes based on the technology will be high-speed, nine-metal-layer logic technologies, dubbed "CMN90" and "CMN90G"--which will include copper-interconnects, low-k dielectrics and other features. The CMN90 process is a high-speed logic process, while the CMN90G is being tailored for core logic devices.

Then in early 2003, TSMC will roll out a wide range of other technologies for the 90-nm node, including an embedded memory process, followed by mixed-signal/RF process. Later in 2003, the company will offer other processes, including a high-speed, low-power and others. The 90-nm process will offer a triple-gate oxide option for design versatility, said TSMC. It is expected to have a core voltage as low as 1.0 volts, a gate length of 45-to-65 nanometers, and a gate delay as low as 7.9 picoseconds for the high-speed option.

On the chip-manufacturing front, TSMC intends to use 193-nm lithography exposure tools to enable the critical layers at the 90-nm node. Phase-shifting and optical proximity correction (OPC) masks will be used to produce minimum feature sizes with the 193-nm tools. The company is reportedly using 193-nm scanners from its long-time partner--ASML Holding N.V. of the Netherlands.

The company also intends to use low-k dielectric for the technology for its copper dual-damscene interconnect process. TSMS said it will use Applied Materials Inc.'s "Black Diamond" low-k materials and chemical vapor deposition (CVD) systems at the 90-nm node, although TSMC is evaluating a number of low-k tools for the 65-nm (0.065-micron) technology node, according to officials today.

TSMC also surprised the audience at the technology symposium by announcing that it will offer an SOI process. The company said it will offer SOI as an option at the 90-nm node for applications requiring higher speeds or lower power features that are possible with silicon-on-insulator substrates.