TI targets 0.09-micron process for production by mid-2003

TI targets 0.09-micron process for production by mid-2003
DALLAS -- Texas Instruments Inc. today announced plans to launch a 0.09-micron logic process into production in the middle of 2003. The technology supports up to nine layers of copper interconnect and will produce than 400 million transistors on a chip, said TI.

The Dallas-based company said its next-generation CMOS logic process features transistors as small as 37 nm (0.037 micron).

TI plans to make available a low-power ASIC design library for the 0.09-micron (90-nm) process by the end of March. A high-performance design library is slated to be available in the third quarter of 2002, as TI prepares for the initial production runs by mid-2003.

The 0.09-micron process will allow TI to push operation frequencies to the multi-GHz range in its own digital signal processors (DSPs) and in UltraSparc RISC processors made for Sun Microsystems Inc., said Yoshi Nishi, senior vice president of research and development at TI. In addition to higher speeds, the process has been developed for integration and circuit optimization matching targeted applications, he said.

The 0.09-micron technology combines copper-metal interconnect and low-k dielectric materials, resulting in the industry's highest SRAM density, according to TI. A six-transistor SRAM design will offer nearly 700 kilobits per mm² in the process, said the company. The process was developed for both 300- and 200-mm wafers fab lines.

Up to nine layers of copper interconnect with OSG (Organo-Silicate Glass) low-k dielectric insulators can be used in the 0.09-micron process. The OSG thin film results in a dielectric constant of 2.8, TI said. The logic process is also based on TI's third-generation of plasma nitrided oxide (PNO) gate materials for core transistors, which the company said have been scaled down to 1.3 nm for the first time. TI said the PNO technology maintains the transistor's reliability while minimizing gate leakage and enabling high-performance speeds at the 90-nm process node.

TI's ASIC libraries will support 1.8-, 2.5- and 3.3-volt I/O interfaces, analog/mixed-signal and RF macros using optimized analog transistors and high-k dielectric capacitors--a first for production logic processes, according to the company.