Advantest moves into engineering test arena with rollout of system

Advantest moves into engineering test arena with rollout of system
SANTA CLARA, Calif. -- Expanding its wings into new markets, Japan's Advantest Corp. is quietly showing customers its new IC engineering test system for debugging and prototyping complex integrated circuits.

The new Design Test Station (DTS) from Advantest was originally announced at the Semicon Japan trade show in December, but the Japanese supplier of automatic test equipment (ATE) provided few details about the tester until now.

The DTS is a 125-MHz, 1,024-pin tester that promises to characterize, debug, prototype and validate complex ICs in only 30 minutes, according to Advantest. The company is "showing" the DTS to prospective customers right now and plans to ship the tester this summer, said Nicholas Konidaris, president and chief executive of Advantest America Corp. The Santa Clara-based company is the U.S. subsidiary of Advantest, the world's largest supplier of ATE systems.

The DTS--which is being developed and built at Advantest America--also represents a new market segment for the company. With the new system, Advantest will compete against Integrated Measurement Systems Inc. (IMS), the pioneer and leader in the IC engineering test market. Beaverton, Ore.-based IMS is a subsidiary of Credence Systems Corp. of Fremont, Calif., which acquired the company last summer (see Aug. 2 story).

Konidaris downplayed the competitive issues in the market, saying the DTS is aimed to solve the ongoing design-to-test problems in the IC market. "We are not going after IMS," Konidaris said. With the DTS, "we are trying to address the design-to-test issues," he told SBN.

The DTS takes a new and different approach to IC debugging, prototyping, verification, added Robert Sauer, president and chief executive of Advantest America R&D Center Inc. Part of Advantest America, the Santa Clara-based R&D organization is directly responsible for developing and building the DTS.

Based on the company's so-called "Event" architecture, the DTS is bundled with software to utilize EDA design data in IC engineering and testing. This capability will reduce verification times by as much as 90%, according to the company.

"The basic DTS is a 125-MHz, 1,024-pin system," Sauer said. "But the DTS takes a different approach. The key point with the DTS is that you are debugging the part using the simulation data," he told SBN.

Advantest is expected to ship the DTS this summer. The company is also developing a separate production tester for system-on-a-chip designs. The tester is being developed in a new, separate organization within Advantest America (see Feb. 12 story).