ST proves diagonal interconnect, plans chips in 2004

ST proves diagonal interconnect, plans chips in 2004
MUNICH, Germany — STMicroelectronics has working silicon of the X Initiative's promised diagonal interconnect regime and is on course to make commercial chips based on diagonal wiring in 2004.

Jean-Pierre, Schoellkopf, a senior expert in central R&D at STMicroelectronics discussed the success on an X Initiative sponsored panel at the DATE exhibition (see March 5 story) having recently produced the first test chips in 130-nanometer process technology.

ST managed to produce 59 working die based on a 25 square millimeter test chip has a comb and serpentine structures in the metal layers, as well as vias linking different layers of metal together. The minimum width was 0.198-micron and the minimum space between metal lines was 0.2121-micron and, significantly the same minimum geometries were used in both the Manhattan and X directions.

Aki Fujimura, general manager of design for manufacturing at Cadence Design Systems Inc., said that this progress from STMicroelectronics is a major step after two years of hard work within the X-Initiative.

The use of the diagonal directions as well as 'Manhattan' rules is expected to allow die area savings of around 20 percent versus Manhattan-only designs.

Schoellkopf said that it was too early for yield figures and possible die area savings. The next stage is to develop a test chip based on proven Manhattan circuitry for direct comparison, he said. "We are pretty confident this is going to work. But yield is yet to be confirmed on more wafers and on real chips. We plan to have a 90-nm test chip soon."

Speaking after the panel session, Schoellkopf, said the company planned to be in a position to offer a diagonal-interconnect enabled process to its designers by the end of the year, but that research had to take one step at a time.