News & Analysis

IBM and partners to cool 3-D IC stacks with microfluids

nic mokhoff

3/15/2010 5:58 PM EDT

MANHASSET, NY — A team of IBM Researchers in collaboration with two Swiss partners are looking to extend Moore's Law another 15 years using 3-D stack architectures with liquid-cooling microchannels.

The collaborative CMOSAIC project will attempt to understand how the latest chip cooling techniques can support a 3D chip architecture. IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) will consider a 3D stack-architecture of multiple cores with a interconnect density from 100 to 10,000 connections per millimeter square.

These connections cooled liquid cooling microchannels 50 microns in diameter between the active chips are the missing links to achieving high-performance computing with future 3D chip stacks, according to the researchers.

The research is warranted for more reasons than extending Moore's Law.

"In the United States, data centers already consume two percent of the electricity available with consumption doubling every five years. In theory, at this rate, a supercomputer in the year 2050 will require the entire production of the United States' energy grid," said Prof. John R. Thome, professor of heat and mass transfer at EPFL and CMOSAIC project coordinator.

The team plans to design microchannels with single-phase liquid and two-phase cooling systems using nano-surfaces that pipe coolants—including water and environmentally-friendly refrigerants—within a few millimeters of the chip to absorb the heat, like a sponge, and draw it away. Once the liquid leaves the circuit in the form of steam, a condenser returns it to a liquid state, where it is then pumped back into the processor, thus completing the cycle.

"Water as a coolant has the ability to capture heat about 4,000 times more efficiently than air, and its heat-transporting properties are also far superior," said Bruno Michel, manager advanced thermal packaging, IBM Research, Zurich.

Chip-level cooling with a water temperature of approximately 60 deg. C is sufficient to keep the chip at operating temperatures well below the maximally allowed 85 deg. C.

The team is leveraging the experience of IBM and ETH in the development of Aquasar, a water-cooled 10 Teraflops supercomputer whose similar collant methods will reduce overall energy consumption by 40 percent.

The participation of the three partners — EPFL, ETHZ and IBM — in CMOSAIC was organized and funded by the Swiss National Science Foundation via the Nano-Tera Research Foundation.





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