Silicon Hive to show SDR processor at MWC

LONDON — Silicon Hive BV (Eindhoven, The Netherlands) has developed a programmable digital RF processor, called the CSP2500. A demonstration is due to be held at the 2010 Mobile World Congress, Barcelona, Spain, featuring Agilent's vector signal generator and signal analyzer with Silicon Hive's HiveFlex CSP2500 processor intellectual property.

The CSP2500 completes Silicon Hive's CSP family of wireless communications processors which also includes the CSP2001 targeting OFDM baseband processing and the CSP2101 optimized for high-performance MIMO applications.

The silicon-proven CSP2500 processor enables C-programmable, multi-standard smart phone transceivers to be written to target EDGE, UMTS, LTE, cdma2000, Wi-Fi and WiMax.

The processor has an array architecture that can exploit both thread-level and VLIW {very long instruction word] parallelism. The architecture also includes a configurable switch matrix, which allows licensees to complement the array processor with hard-wired accelerators.

"The cell-based array architecture of CSP2500, combined with synchronous stream-based processing, forms the ideal platform for area and power efficient, multi-standard digital radio frequency processing in future mobile smart phones and makes verification of the functionality much easier than in asynchronous alternatives," said Martti Forsell, chief research scientist at VTT and Adjunct Professor at the University of Oulu, Finland, in a statement issued by Silicon Hive.

"Programmable multi-standard transceivers offer smartphone SoC manufacturers the ability to optimize and differentiate their own digital radio frequency implementation on a flexible platform and to select the best performance/area/power trade-offs for a given application," said Jeroen Leijten, CTO of Silicon Hive, in the same statement.

The HiveFlex CSP2500 processor is supported by Silicon Hive's HiveCC software development kit and is available for licensing.

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