Group's 'interoperable' analog flow turns up heat on Cadence

ANAHEIM, Calif. — The once-sleepy analog EDA market is suddenly generating a lot of buzz, as a number of forces combine to advance the technology and threaten Cadence Design Systems Inc.'s stranglehold.

Ciranova, Magma, Synopsys and others are entering the revived analog EDA fray with tools that compete against Cadence's. But the biggest jolt for both the market leader and its rivals occurred this week at the Design Automation Conference (DAC) here, when Taiwan Semiconductor Manufacturing Co. Ltd. threw its weight behind a fledgling alliance and announced a major thrust in analog and mixed-signal design.

During the run-up to DAC, silicon foundry giant TSMC joined the Interoperable PDK Libraries industry alliance. The IPL group, which includes Magma, Mentor, Synopsys and other tool and intellectual- property vendors, is pushing for a standard foundry process design kit (PDK). If and when this PDK technology hits the commercial market, it will function as an "interoperable" reference flow for analog and custom IC design, backers say.

Today's PDKs are proprietary and incompatible. The IPL-backed version is said to support analog layout tools from all vendors over a common database, and to interoperate with Cadence's proprietary analog environment.

But some view the IPL-backed flow as a competitive threat to Cadence's analog EDA tool suite, dubbed Virtuoso. Ca- dence has refused to join the IPL alliance, saying the rival technology provides little value for analog designers.

At DAC, the alliance got a shot in the arm when TSMC said it would offer a PDK based on the IPL technology for 65- and 45-nanometer chip designs in the first half of 2009. The foundry giant will continue to support Cadence's proprietary analog EDA environment as well. Other foundries and chip makers are expected to jump on the bandwagon, attracted by the IPL PDK's promise to reduce costs and accelerate analog/custom IC. design.

"Cadence's [analog EDA] franchise has been broken," said Gary Smith, co-founder and chief analyst with Gary Smith EDA, a market research firm.

Whereas in the past, analog EDA was "captive to one supplier," now the "world has opened up" for new and competitive tool vendors, said Aart de Geus, chief executive and chairman of Synopsys Inc.

The stakes are high in analog EDA, a $400 million business, according to Gary Smith EDA. Cadence is estimated to own up to an 80 percent share. Some 25 percent of Cadence's total sales are derived from custom IC tools, including analog.

There are still some major challenges in cracking Cadence's dominance. Creating an inoperable PDK sounds good on paper, but the question is whether the stodgy analog world will buy it.

With TSMC backing the IPL alliance, the technology could fly. One thing is certain: "The market is really moving toward mixed signal," said Walden Rhines, chairman and chief executive of Mentor Graphics Corp. "The digital chip designers are integrating more and more analog" functions on the same chip.

Analog-digital divide

Several years ago, the digital world embraced tools that were highly automated, thereby boosting the development of complex SoC designs at competitive costs. In contrast, analog design has been stuck in the slow and painful manual world.

In simple terms, designers arrange transistor-level components--capacitors, diodes and the like--in a schematic layout. The layout is generated manually via a menu-driven programming function, based on a parameterized-cell (p-cell) methodology. The p-cell libraries include the various transistor-level components.

Cadence's Virtuoso tool suite houses the schematic-layout function, p-cell libraries and simulation tools over the industry-standard OpenAccess database. But Cadence's p-cell libraries are written in a proprietary language called Skill. This fact locks customers into Virtuoso.