Next-gen line cards take careful design

High-speed line cards have become a ubiquitous offering in the OEM's portfolio, used to lure, secure and assure new prospects or loyal customers of advances in silicon technology. Further, the ability to scale and upgrade system capacity in the field has become one of the key factors that carriers consider in selecting equipment vendors. The challenge is to provide a cost-effective approach for today's network traffic while enabling a linear cost model for future expansion. But, is the designed switching capacity a limiting factor in the deployment of ever-greater line card capacity? The answer is contingent on the line card design.

In a typical multiservice switching-platform design, the high-speed line card includes optical-electrical-optical transceivers; clock and data recovery devices; framers or mappers; a microprocessor for operation, administration, maintenance and provisioning; and high-speed serializer/deserializers that connect to the centralized time-division multiple access (TDM) switching plane. The continuous size reduction in silicon manufacturing geometry, from 130 to 90 nanometers in the near future, promises higher framer capacity and lower power consumption. But increased framer capacity without support for more processing functionality poses several design challenges.

First, to address the need for various network services, a high-speed line card must flexibly combine OC-192, OC-48 and OC-12 ports with small-form-factor pluggable optics. A multirate 10-Gbit framer must be able to handle up to 16 different time domains, provide full transport overhead processing for all 16 interfaces, and maintain alarm and performance monitoring for 192 STS-1 paths.

Second, for the SDH market, the system must deliver switching granularity at the VC-3 level using TU-3/Tug-3 mapping that is not available in the Sonet world. Thus, the framer must provide high-order pointer processing for AU-4 mapping as well as low-order pointer processing for TU-3 mapping. Adding the numbers, this translates to 64 high-order and 192 low-order pointer-processing state machines, as well as 256 path-monitoring processes.

Third, the ability to support network protection mechanisms such as bidirectional line-switched ring (BLSR) and unidirectional path-switched ring (UPSR) must be taken into consideration. The BLSR switchover mechanism relies on the framer's ability to debounce, process and generate the K1K2 bytes that indicate a line failure. The protection-switching mechanism can be implemented locally on the line card or the burden can be shifted to the main switching plane.

Path- and alarm-monitoring features play a key role in supporting the UPSR switchover mechanism. The framer must provide event notifications to the common switching matrix that is responsible for switching from the working to the protected channel. For path protection at the STS-1 level, those events include the configurable signal degrade threshold indication based on the accumulated B3 bit error rate, payload defect indication, signal fail based on configurable threshold indication of the same B3 bit error rate and path unavailability conditions.

The alarm conditions become more complex if virtual-tributary (VT) switching is supported. Not only must STS-1 alarms and events be conveyed to the switching matrix, the events must also be correlated down to VT-level alarms. Also, similar performance degradation or tributary unavailability alarms must be monitored for all tributaries. This results in the staggering value of 5,376 VT-level monitors for an OC-192/STM-64 line. Clearly, relying on the software to provide the required path- or VT-monitoring functionality puts an undue burden on the software architecture.

In terms of system scalability, the use of a centralized switching architecture requires a high initial cost to deploy the full switching capacity while limiting the system scaling capability for the future. High-speed line cards can be added to the system as long as the total system switching capacity is not exceeded.

Next-generation designs

This architecture conundrum can be addressed successfully if system vendors can flexibly enhance the central switching with local, embedded line card switching.

Based on the services offered, line cards may include data switching for Ethernet/generic framing procedure services or TDM switching with either STS-1/VC-3 or VT1.5/VC-12 granularity. This approach to high-speed line card design lets the system grow beyond the capacity of its central switch by retrofitting existing system designs with flexible framer and mapper devices that integrate full nonblocking switching features.

This next generation of framers and mappers will not only increase system capacity but also provide additional processing features required by new Sonet/SDH network services. Pointer processing to at least VC-3 containers must be fully supported in hardware. Minimal software interaction, mainly for system configuration, is needed for all standards-based performance monitoring and alarm integration.

Integrating the nonblocking switching functionality with the framer allows the system to scale beyond the capacity of the main switching plane. Local grooming is then performed for traffic limited to the interfaces residing on the same line card, while the main switching plane is used for line-card-to-line-card cross-connect.

Embedded line card grooming also reduces the capacity needed to handle duplicate paths. The alarm conditions at the STS-1/VC-3 level are locally detected by the high-speed framer and are immediately available to the integrated switch to select between working and protected paths. The downside is that the framers must switch more than 192 STS-1 channels for a 10-Gbit line card.

Automatic protection switching (APS) requires the framer to interface to the working OC-192 port and to the protection port, typically residing on an adjacent mate line card. The total embedded-switching capacity must be equal to no less than three times the capacity of the network interface, accounting for the APS traffic and the traffic to and from the main STS-1 switching card.

With the gain in popularity of virtual concatenation (Vcat) services, system designers must take into consideration the level of network and system protection offered for the whole Vcat group rather than its individual channels. The framer should be able to correlate the alarm condition of an individual channel to the working condition of the group that was set up using the link capacity adjustment scheme. In such cases, the event that would normally trigger switchover of an individual channel would initiate switchover of the entire group. Finally, adding embedded switching to the line card can also provide VT1.5 grooming capabilities not available in STS-1 switching platforms and allow the system to add VT grooming capabilities as needed.

Radu Iorgulescu is director of product management at TranSwitch Corp. (Shelton, Conn.).

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