Understanding jitter issues in OC-48/OC-192 line cards

The telecommunications industry is now seeing the deployment of more complex network architectures and higher-speed Sonet/SDH transmission systems, particularly those operating at OC-48 and OC-192 rates. For designers, achieving accurate network timing and synchronization on these higher-speed systems presents a far more challenging task than ever before.

In Sonet/SDH systems, jitter generation, jitter transfer and jitter tolerance demand consideration from line card designers. A number of standards organizations, such as American National Standards Institute's (ANSI) T1.101-1999, Telcordia's GR-253-CORE and the International Telecommunication Union's (ITU) T G.813, have issued parameters for jitter.

For a line card used in a system where there are primary and secondary references distributed via the backplane, either a digital phase-locked loop (DPLL) or a simple multiplexer can be used to switch the two references from the backplane.

A DPLL offers several advantages, including hitless reference switching between the primary and secondary timing card references, as well as short-term holdover. An analog PLL (APLL) can then be used to filter the jitter on the output of the DPLL, which attenuates the in-band jitter to meet system compliance requirements with substantial margin.

In comparison, a simple mux acts as a reference switch between the primary and the secondary references, and the phase difference between the two clocks will be transmitted through the APLL. As a result, the output clocks will experience a phase hit during reference switching.

When hitless reference switching and ultralow jitter are required, designers must use a combination of a DPLL and an APLL. When choosing the combination of a DPLL and an APLL, system designers must be aware of the phase noise of the DPLL so that the right loop filter is chosen for the APLL.

As seen in the accompanying figure, from 100 Hz up to 200 kHz the DPLL1 has higher noise than the DPLL2. To filter the noise from DPLL1, the system designer will have to use an APLL with the corner frequency of the loop filter as low as possible, around 1 kHz. All of the low-frequency noise below 1 kHz will still go through the system and contribute to the jitter at the output of the APLL. In addition, the lower the corner frequency of the loop filter for the APLL, the more of its own voltage-controlled oscillator noise will be added to the output.

Since DPLL2 has lower phase noise at low frequencies, the system designer can open up the loop filter of the APLL. The analog loop filter in this case could be set to 10 kHz, so all of the high-frequency jitter is filtered out, and the low-frequency behavior of the combination of the APLL and the DPLL2 will operate much better than the combination of the APLL and DPLL1.

In the Sonet/SDH line card described here, the APLL is providing the clocks to several components on the board. All components on the data path downstream of the clock will add jitter to the outgoing Sonet/SDH signal. The APLL must be designed to filter the jitter with enough margin to allow the whole system to meet jitter generation standards requirements. Margins of 50 percent to 75 percent are expected from the APLLs, depending on the system.

The Sonet/SDH system must also comply with the jitter tolerance and jitter transfer masks as described in ANSI standards, Telcordia requirements and ITU requirements. Jitter transfer, jitter tolerance and jitter generation are interdependent — they are all related with the bandwidth of the APLL — meaning designers must make trade-offs in order to produce a system that meets all applicable industry specifications.

Board issues

The use of good practice for decoupling and bypassing of DC power buses in printed circuit boards is essential for effective control of jitter in clock circuits.

Noise energy on circuit boards can translate into jitter on clocked signals if it is not filtered. Supply noise entering a device via power pins produces small momentary shifts in device input switching thresholds and on output signal transitions. Noise produced by on-board switching power supplies has energy, in the approximate frequency range of 100 kHz to 5 MHz. The noise produced by digital switching circuits has energy that dominates in frequencies ranging from 10 MHz to 500 MHz and higher. Both types of noise may contribute to jitter in clock signals on the board.

In the case of a Sonet/SDH line card's transmit data path, jitter is cumulative in the data signal between the point at which the signal is retimed by the serializer, and the point at which it arrives at the line card's optical connector as a light wave. The DPLL, APLL, serializer/deserializer and electro-optical device each contribute to the total transmitted jitter. In effect, each device consumes a portion of the implicit jitter budget as dictated by the applicable standards. Contributions to jitter by power buses should be reduced to the greatest reasonable extent.

The overall strategy for dealing with switching supply noise will vary according to the circuit design and its power requirements. It is an important design consideration to have a power distribution and filtering strategy that takes into account the various sources of power noise, along with the expected noise sensitivities of affected circuits.

There are a number of strategies that can be employed to isolate switching power supply noise from affected circuits. For example, designers can provide an additional low-pass filter switching supply output between the output pins and power bus. A second-order low-pass filter with passband a decade or more lower than the switching frequency can be effective, but passive power components add to board cost and consume board space. Alternatively, the design could feature low-pass filter power rails on a localized basis using RC or RLC filters where needed to isolate sensitive clocking circuits. A simple low-pass RC filter is effective if the desired bandwidth can be achieved while limiting the DC voltage drop to acceptable levels. Another strategy to isolate noise from circuits is to use linear regulators to remove power supply ripple in some cases. These linear regulators are not particularly efficient, however, and therefore may be suitable for use in very low power circuits.

In addition to isolating power supply switching noise, designers must also concern themselves with reducing digital-circuit switching noise in a Sonet/SDH line card design. The switching activity of digital circuits emits high-frequency noise that is conducted into power planes. The total ac noise on a power rail is the cumulative emission of devices to which it is connected, in particular line drivers, buffers and integrated circuits that draw significant current, or switch the states of multiple outputs simultaneously and produce instantaneous changes in current on power rails.

The first line of defense against power noise for clocking circuits is optimal selection and layout of broadband decoupling capacitors. Capacitors must meet design requirements in terms of storage capacity, voltage rating and frequency response. These components filter noise by providing a low-impedance path between power and ground. In order to maintain constant voltage, they must also source and sink switching current to the device. Finally, decoupling capacitors must provide a signal return path between power and ground buses for high-speed signals.

Designers could further improve the isolation of digital switching noise by creating small local power buses, separated from the power distribution plane by low-pass filters constructed with passive components. A simple RC or LC filter with a pass band of up to 1 MHz will usually attenuate switching noise effectively. Further reduction of the overall noise level on the power distribution buses is achieved by blocking the switching noise emitted by device power pins. PI filter structures can be employed to block the transmission of power noise in both directions between the power bus and digital IC devices.

Russ Byers is a hardware engineer and Silvana Rodrigues is a system architect at Zarlink Semiconductor's Timing and Synchronization group (Ottawa).

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