AdvancedTCA helps NPU-based redesigns

The popularity of network-process-ing units is partly due to the fact that they can be reprogrammed, with the associated benefit of design reuse. So when new standards are approved or new functionality is developed, software can be downloaded into the NPU and the system upgraded with minimal impact on the network.

In reality, however, that benefit is hampered by limitations imposed by outdated and proprietary system designs. The new capabilities in question might require more components, which affects board layout and possibly power draw. Or they might require a new data flow, which changes the processing order or requires data to flow back to a device that has previously processed it. Thus, the reprogramming advantage equals a board re-spin and any time-to-market or technology benefits are negated.

The Advanced Telecom Computing Architecture, the first-ever standard for the system design of central-office-based networking equipment and a switch-based interconnect scheme, can move CO-targeted designs closer to the goal of design reuse. AdvancedTCA is a perfect match for NPU-based designs and sets out a complete design architecture governing mechanical, power, thermal, management, data transport, mezzanine cards and regulatory aspects of networking equipment.

Inside the architecture

The architecture is based on the PCI Industrial Computer Manufacturers Group (PICMG) specification 3.0 and calls for a 12U-high chassis with server blades that are 8U high by 280 mm deep with a 1.2-inch pitch. Total board power can be up to 200 watts with forced-air cooling in the bottom of the chassis. Power comes from a backplane standard that allows for distribution of 48 volts of dc power to all the cards.

Multiple backplane standards and architectures are supported, including Ethernet, PCI Express and Infiniband in dual-star or mesh interconnection, with the ability to handle multiple links up to 40 Gbits/second (for a total capacity as high as 240 Tbits/s) and with 99.999 percent uptime and CO-level quality-of-service.

The flexibility of the architecture comes from the advanced mezzanine cards that are called out in the ATCA AMC specification. Up to four AMCs can be on a card and these can support Layer 4 to 7 functionality like packet classification or security. AMCs can also support add-on media options like fiber-optic ports, or added switching, routing or packet-processing capabilities.

The range of functionality provided for by the AMCs can extend to storage-area networking, added computing and other functionality. Some observers predict that AMC capability will be used to deliver universal-access devices that can be deployed to support digital subscriber line, cable modem, Wi-Fi and others from a single chassis, merely by interchanging the AMCs. Enabling that flexibility will require a switched interconnect that can facilitate the changes in data flow and chip interconnection when a new AMC is added to a board. The standard allows the system designer to make the choice of the appropriate board-level interconnect scheme for the application.

NPU-based designs that move data at speeds above 1 Gbit/s are being limited by the bus fan-out and bus clock distribution. Some designs have moved to a high-speed, low-voltage differential-signaling- or serializer/deserializer-based point-to-point interconnects because they don't have the bottlenecks associated with the shared bus. But these designs have traditionally daisy-chained the chips together into fixed ingress and egress paths. There's no flexibility for interconnecting these data paths or for data flow back to a processor through which it has already flowed.

An example of these complex data flows is shown in the diagram, where a packet flows first through a framer for packet parsing, then to the NPU, where the packet is classified and the destination information is resolved. Then the packet is delivered to the traffic manager to be scheduled for delivery across the backplane, through the switch fabric and to the appropriate destination. This orderly flow changes when an encrypted frame arrives at the NPU, requiring additional processing. The packet is sent to the decryption co-processor by the NPU. After decryption, the packet flows back to the NPU and enters the normal flow of data.

In addition to this flow-back support, switches are required in this application to simplify the support of modularity. As advanced mezzanine cards are removed from the system, the board-level switch can terminate the unused ports and intelligently redirect the data originally flowing to that attached card.

Switches are not all equal

Switches for this application should have low latency and high throughput. The introduction of a switch function between all the connected devices should be transparent to the application. The architecture cannot introduce head-of-line blocking into the system. Stalled traffic must not interfere with unrelated traffic that is not stalled. This can be accomplished with significant overspeed in the switch core, large, partitioned buffers and efficient flow control.

Buffer size and configurability are important in eliminating head-of-line blocking. But larger isn't always better, since a low-latency switch fabric and highly efficient flow control scheme can reduce the requirement for buffer space. Any-to-any device connectivity comes from channel-mapping capability that can direct traffic from any input port through the switch to any output port based on their ingress and egress channel IDs.

Switching is possible for many popular protocols and interface standards including SPI-4.2, XAUI, Hypertransport, RapidIO, PCI Express and Advanced Switching. Some standards, such as SPI-4.2, leverage the concept of channels to control the flow of traffic, maintain efficient switching and eliminate head-of-line blocking. Others provide flow control based on the concept of unique conversations, which often requires more sophistication and processing power in the switch element to classify packets.

Future-generation switches will simultaneously support several of these protocols and interface standards, allowing mix-and-match use of NPUs with different framers, traffic managers, processors and control processors.

The AdvancedTCA standard provides a clear platform for supporting next-generation NPU designs. Switched board-level interconnects provide the chip-level communications and flexibility needed to support complex data flows and related system modularity. Used together, they can remove the limitations to design reprogrammability and reuse that have remained a promise for too long.

Uri Cummings is co-founder and vice president of product development at Fulcrum Microsystems (Calabasas Hills, Calif.).

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