News & Analysis
A new approach to modeling network processors
Vin Ratford
2/5/2004 5:23 PM EST
In his final "Tool Talk" column of 2003, Richard Goering, EE Times' group editorial director, saluted the courageous spirit of designers who last year staked their claims in incredibly shrinking technology nodes. Many of them boldly faced power and speed management challenges that migrate along with the technology from .18um to .13um. A few intrepid designers even braved the mostly uncharted waters of 90nm. "If power isn't scary enough," wrote Goering, "the manufacturing issues that loom at 90nm and below are downright terrifying."
And, we would add, when the design happens to be an application-specific network processor, it must run at high speeds. It must have tens of mbits of embedded SRAM, tens of millions of gates of register transfer level (RTL) code, and massive amounts of high-speed I/O. Only then can a network processor design team be reasonably certain that fear will serve as the surrogate mother of invention.
Uncertainty— or the fear of the unknown — is a classic motivator. Indeed, smart semiconductor companies engaged in designing network processors must make well-informed, carefully calculated decisions at each juncture if they hope to meet their critical area, power, speed, and yield targets.
Until recently, such companies were forced to rely upon their own experience to guide them through these decisions. Meanwhile, the network processor design team would create an Excel spreadsheet with which to model key characteristics of the network processor design and the intellectual property (IP) it uses. Teams would search through IP catalogs, solicit manufacturers estimates for area, power, speed of the IP, process information for each technology node and process variant, and after months of work, arrive at an answer.
A new approach is emerging, called the Silicon Virtual Model, and it's being implemented in select companies today. At its most basic level, the Silicon Virtual Model takes many of the uncertainties surrounding network processor development and makes them predictable. These uncertainties could include: ASIC or Customer owned tooling (COT); optimal technology node and process variant; the availability of soft and hard IP and libraries; how much repair is needed in the memory and how to implement it.
A Silicon Virtual Model allows designers to quickly assemble a mock-up using internal and third-party IP to help make key decisions about the network processor. The resulting model can be used to defeat uncertainty by exploring likely scenarios and answering key questions such as:
The Silicon Virtual Model is the design for a given set of assumptions. It includes a detailed datasheet with all the key electrical and economic factors ( speed, active power, leakage, area, yield and die cost. It also includes a floorplan of what the network processor should look like and a bill of materials (BOM) for the IP, along with useable charts and graphs.
To create the Silicon Virtual Model, the designer enters key specifications about the chip into a specification cockpit, selects third-party IP from a comprehensive IP catalog, and describes any proprietary network processor IP.
Once these steps have been taken, the designer clicks "Estimate" and the Silicon Virtual Model is created and displayed. Estimates are available quickly, allowing the designer to explore different combinations of IP, process parameters, and architectures, and determine the optimal mix.
A Silicon Virtual Model is created by assessing a centralized database of IP data located on a server each time Estimate occurs. Servers containing the data are eitherGeneric — that is, not tied to any particular process but are typical or often used — or branded, which contains IP data for a specific vendor/foundry/process combination. This allows a designer to experiment with various choices before a foundry or IP vendor is chosen.
To allow for rapid Estimation, the Silicon Virtual Model utilizes a Technology Macro Model that has beenprepared in advance fromphysical data — .lef, .lib — for each process technology and variant. For example, the SRAM data isgenerated from the actual memory compilers themselves, ensuring a high level of correlation.
The designer can select from hundreds of different memory compiler types and determine the optimum configurations in the context of a design. They can then look at total memory yield and begin to include repairable memories until yield targets are met. The Technology Macro Model includes detailed information about not just the memories but routing overhead, bist structures andthe different repair options. A typical Network Processor contains hundreds of unique SRAM configurations that are constantly being modified. Together they often consume over half of the die area.
For logic elements, the Technology Macro Model is created from the standard cell library data, again ensuring it correlates to silicon. Key parameters are modeled including leakage, area, cell and routing utilization, as defined by IP vendors with the designer able to "override" these defaults. In this way, key assumptions that impact the design are captured and annotated.
Most of the Network Processor's target specs will be determined by the choice of library, memories and the efficiency of the RTL. Initially, gate count estimates are adequate to create the Silicon Virtual Model. As the RTL details become known, designers can iterate on the model and determine the impact on the overall design. Proprietary or hardened IP can be entered directly or read in via a .csv file from an existing IP repository.
Finally, during the Estimate phase, a floorplan of the IC is created. This allows the Silicon Virtual Model to add "details" about clock trees, wire loading and capacitance so that the Estimates reflect what is likely to occur for a given implementation. This type of detail, accuracy and iterative design is not possible given the current paper, pencil and spreadsheet approach.
Vin Ratford is president of Giga Scale Integration Corp. (Cupertino, Calif.)
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