Addressing packaging concerns of low-k silicon

Addressing packaging concerns of low-k silicon
Ultrafine feature sizes and high performance requirements have necessitated the integration of low-k dielectrics on silicon-level interconnects that are mechanically weaker than previous-generation materials, a fact that has been recognized to be an industrywide issue. The inherently weaker nature of the low-k dielectric material can pose significant challenges to downstream electronic-packaging processes and materials.

Low-k materials are, by definition, those semiconductor-grade insulating materials that have a dielectric constant ("k") lower than 2.9. The need for lead-free solders and environmentally friendly materials has further increased the risks involved in packaging low-k silicon. The success of the new silicon technologies will hinge on timely resolution of these novel packaging-related issues.

Most of the problems that show up during low-k assembly can be traced to two issues: typically lower interfacial-adhesion strength in a silicon stackup, and weaker bulk-mechanical and fracture-strength properties. These weaknesses are well known in the industry and many research efforts are under way in assembly sites worldwide to compensate for them or to make them more tolerable.

The areas of greatest concern in the packaging of copper, low-k silicon and Pb-free solders are wafer sawing, wire bonding, and chip-to-package and package-to-customer board interconnects (flip-chip solder bumps and package BGA solder balls). Paying close attention to these process steps and optimizing their parameters will protect the low-k silicon from damage and will provide highly yielding, highly reliable manufacturing processes.

Poor adhesion of silicon materials can show up as silicon delaminations or peel-off at wafer saw and wire bond. Delamination is a disconnection or crack between two layers within a silicon stackup. From a mechanical viewpoint, these gaps are weak spots in the silicon which can be exacerbated to the point where silicon interfaces are pulled apart by packaging- and assembly-induced forces.

Sawing through 90-nanometer low-k materials has yielded more silicon damage than was observed with previous silicon nodes, including 130 nm. It has been shown that these interfacial cracks travel for the most part perpendicular to the scribe street and can in some instances broach the seal that envelops the die. The die seal serves in part as a barrier to moisture and ionic contamination, and its structural integrity is a key component in ensuring package reliability.

During dicing of low-k materials using mechanical sawing, it is a challenge to ensure that any silicon cracks do not propagate past the scribe seals of the dice and end up in the active area of the circuits. The wafer saw suppliers are actively working with their customers to provide the best solutions and to minimize the occurrence of this silicon damage. Specially designed saw blades for low-k silicon are now on the market. The use of these blades, plus finely tuned saw process parameters developed over many learning cycles, will be required to achieve acceptable results. The fact that silicon delaminations are present in the scribe street is not necessarily cause for action. Each copper, low-k silicon manufacturer must assess the frequency and severity of the damage and decide whether there is any risk to its products. Silicon cracks can grow larger and elongate over time with repeated heating-cooling cycles, leading to possible electrical failure of the packaged unit.

The wafer saw spindle and index speeds are critical to the overall saw quality and in reducing the frequency of peeling defects. Optimizing these machine parameters in combination with the right choice of saw blade will lower the chances that silicon delaminations will occur. Another solution is redesigning the scribe street to make it more "low-k friendly." The test structures and alignment markers found in the scribe line greatly influence the incidence of delaminations. Optimizing their design for low-k applications is advised.

Due to the problems reported in mechanically sawing low-k wafers, the use of lasers to complement or replace the mechanical saw is becoming more of a reality as several suppliers worldwide are earnestly developing such a process. The laser saw has shown the potential to lessen scribe line damage, but the process cycle times and capital costs are higher than in traditional mechanical sawing, which is not totally unexpected with a new technology.

The low-k silicon stack is mechanically less forgiving than past silicon nodes, which presents unique challenges to developing a robust bond process. A bond engineer must take a different approach and thought process to wire-bonding low-k dielectrics. The softer, spongier low-k materials drastically affect the dynamic interactions of the bonder against the top surface bond pad.

The critical parameters for wire-bonding copper, low-k silicon are ultrasonic energy, time and force. Experiments conducted at TI revealed interdependencies among these three factors. One commonly observed defect from bonding low-k silicon is lifted metal or silicon chip-out, which can happen during the actual bonding process or during postbond wire pull analysis. Adjusting the bonder parameters can provide marginal assistance in resolving this defect, but the fix with the largest payback is often improving the adhesion of the silicon layers, since the material properties of the dielectrics cannot be changed.

The switch from eutectic lead-tin (PbSn) solders to Pb-free solders (SnAg, SnCu, SnAgCu) as a response to worldwide environmental legislation can create a predicament for BGA solder balls (package-to-customer board connection) and flip-chip solder bumps (chip-to-package connection). Pb-free solders are stiffer than eutectic solders and will, therefore, transfer extra packaging stresses to the silicon. Also, the peak reflow temperature of the Pb-free solders (~250C vs. 215C for eutectic) also increases the stress applied to the package and silicon because of the larger temperature difference as the package cools to room temperature. It is the differing thermal behavior or expansion of the various materials that creates these sometimes excessive mechanical stresses. If one does not manage the stresses applied to the silicon, the stresses can exceed the low fracture strength of the low-k dielectrics, resulting in cohesive or adhesive failures. These failures are manifested as cracks within the dielectrics or delaminations along interfaces.

The choice of underfill materials for flip-chip packages designed with Pb-free solders and low-k silicon is crucial to mitigating the stresses. Underfills are organic epoxies typically applied through capillary action between the chip and package substrate. If formulated correctly, the underfills distribute the package- and assembly-induced stresses over a wider area, avoiding placing all the stress on the smaller bump interconnections. The elastic modulus and thermal properties of the underfill must be controlled to match the silicon properties so as to ensure no silicon damage occurs.

TI has taken all of these lessons and applied them in developing packaging technologies that have kept pace with silicon process development to enable on-time delivery of cost-effective and reliable solutions with desired form factors. This trend is accentuated on the 90-nm silicon process, wherein TI's packaging activities are aligned with silicon process development and learning cycles.

Greg Hotchkiss and Vish Sundararaman are technology process engineers with Texas Instruments Inc. (Dallas).