News & Analysis
Applied makes 65-nm X-architecture test chip
David Lammers
2/25/2004 10:14 AM EST
AUSTIN, Texas — Applied Materials Inc., working with Cadence Design Systems, Inc., has made a 65-nm test chip using diagonal as well as traditional right-angle Manhattan interconnects.
The X Initiative consortium said Wednesday (Feb. 25) that Applied created the first 65-nm X-architecture chip at the company's technology center in Sunnyvale, Calif. Applied fabricated an X-architecture 90-nm test chip last summer.
The companies will discuss the challenges involved with the X-architecture in two papers to be presented Thursday morning at the SPIE lithography conference being held in San Jose this week. The X architecture supports designs with significantly less wire and fewer vias, while improving speed, power, and costs, the consortium said.
The test chips "provides further confirmation of the manufacturing readiness and scalability of X Architecture designs for future process nodes," said John T.C. Lee, general manager of Applied Materials' Maydan Technology Center. The approach leverages standard design, verification, mask making, processing, and inspection disciplines, he added.
Cadence provided the test structure design and chipvalidation tools, and a Canon 193-nm scanner was used for the project.
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