Using RTL floorplanning to budget nanometer designs

Using RTL floorplanning to budget nanometer designs
Today's nanometer technology design activity provides a means to capture functional intent using a top-down methodology. A key factor in successful timing closure is setting good physical and timing constraints as the design process commences.

Constraints are especially important in hierarchical design where good block-level constraints improve the ability to implement the blocks separately and still achieve overall timing closure efficiently. Unfortunately, the floorplanning activity needed to provide the timing and area insight is a bottom-up process that can't occur until after synthesis since most floorplanners require gate-level input to operate.

As such, the generation of top-level constraints for complex designs is a tedious, iterative process that consumes significant engineering resources. Often, to avoid iterations, the assumptions used in a floorplanning task on a new design are best-guess estimates from earlier designs coupled with fudge-factors built in to account for process and geometry changes. This bottom-up process requires designers to make assumptions regarding the block-level budgets before the design commences. Often these assumptions at the block level are overly optimistic relative to the true view from the top level.

For example, block-to-block paths and "snake paths" (those paths that initiate in one block and transverse through two or more blocks) add significant challenges to timing closure at the top level.

The register transfer level (RTL) floorplanning process begins by reading the RTL design and some hints about block positions, aspect ratios, and area utilization. In combination with timing pragmas, one can create black box models for RTL code that have not yet been written. Hand-driven and automatic optimization can then occur on this initial seed floorplan. Macro cells can be auto-placed or pre-placed for top-down or bottom-up design approaches. During the timing analysis process, accuracy is maintained in multiple ways. Using the same .lib, LEF, and Apollo input files used by standard implementation flows ensures timing accuracy. Netlist accuracy is provided by using the same flip-flop, latch, and inferences as in full synthesis.

Ideally, the generation of top-level constraints and block-level timing budgets would occur early in the design process and would be extracted directly from the RTL with an awareness of the synthesis and physical optimizations that will occur later. The planning process would also allow for black box placeholders for hard intellectual property (IP), memories and undeveloped logic, and would have accurate area relative to the placed and sized gate netlist. Based on an initial placement, the floorplanner can generate routes that give an accurate prediction of the final parasitics. In turn, this data can then be used to produce more accurate wire load models and give early identification of critical nets without having to run synthesis.

An ideal environment for RTL floorplanning would be built around RTL timing analysis combined with cross probing capabilities. Within the InTime environment, for example, a work function is used as the abstraction of an RTL code fragment. Each work function provides an area estimate and a timing model. The placement of work functions gives an approximate physical location to the gates attributed by the work function. The physical location is then used to derive routing parasitics so that one has a complete and accurate timing view for debug. InTime's Time Planner product provides these core features as well as the integrated schematics and RTL code linkages necessary to perform timing debug and floorplan optimization. Block-level budgets can be created directly from the RTL code once the physical aspects of the floorplan have been established.

Once the floorplan is generated, synthesis scripts are automatically created using the budgets and parasitics from the floorplan. Also created are accurate set-load models and block-specific wire-load models that will guide third party synthesis engines. Where users are interested in feeding out to gate-level floorplanners or physically-aware synthesis tools, there are linkages through industry standard formats such as LEF, DEF and PDEF or even proprietary floorplan definition formats. The use of RTL floorplanning early in the design flow allows these expensive back-end tools to be given higher quality input so fewer design flow iterations are necessary.

By using RTL floorplanning and RTL-level static timing analysis the hand-off from the RTL design team into the next stage in the flow is improved and simplified. The transition is:

Cleaner

Contains more accurate and usable design data

Provides design constraints that speed the flow through logic synthesis

The resulting RTL-based flow has a positive impact by reducing design debug iterations. RTL floorplanning and static timing analysis capability brings a top-down methodology to the process of timing closure and synthesis constraint generation. It allows design engineers to perform meaningful analysis on their RTL code during the early stages of the design cycle without having to guess or wait a turn through synthesis. By working at the RTL level, the generation of constraints and budgets for logic synthesis occurs faster and earlier in the process than the current method. This provides a better "seed" to physically-aware synthesis applications. The result is faster synthesis and improved post-synthesis circuit performance. Furthermore, by performing floorplanning at RTL users can achieve turnaround times 40x to 50x faster than conventional gate-level approaches.

Wendell Baker is Vice President of Engineering at InTime Software, Inc., (Cupertino, Calif.)