Tools address the whole package

As IC speeds continue to climb well into the gigahertz range, system designers are finding that the new obstacles they must overcome to interconnect ICs to packages and packages to printed-circuit boards are blocking their ability to fully utilize these increases in chip speed.

Though a plethora of design and verification tools exist for IC design, IC package design and pc-board design discretely, the EDA industry has only just begun to address the links among these three disciplines. One of the biggest barriers to the creation of IC and package tools and methodology-let alone chip, package and pc-board co-design or co-verification tools and methodology-is that few EDA companies offer tool sets for all three disciplines.

Cadence Design Systems Inc. is widely seen as the most advanced in this area. The company currently offers modeling and analysis technology to help designers speed signals from package to board and is working on adding IC to the mix. In this special report, Cadence talks about its offering, how it is deployed and what the company plans to do next.

But as we will read in this In Focus report, there is both a demand and a market opportunity for EDA vendors to do much more.

Marco Cassale-Rossi, STMicroelectronics' EDA partnership manager, pleads in his contributed article for the EDA industry to do more work in the area of IC and package co-design and co-verification. For their part, three Intel engineers discuss how a complete system view of IC-to-package-to-board is needed, and how they modeled and then implemented a front-side bus through IC, package and board on a recent PC design, with the assistance of point tools.

Advanced Wave Research authors further outline the challenges of IC-package-board co-design and verification and describe what type of tool set is needed. Articles from Atmel, Xilinx and Mentor Graphics tell how FPGA vendors have addressed the problem of FPGA-to-package-to-board co-design. And TDA Systems' Dima Smolyansky presents TDR-based analysis techniques that allow a gigabit-system designer to produce more accurate models for gigabit interconnect.