Speedy FPGAs need IC/package co-design

Until recently, chip designers mainly focused on optimizing their designs within the silicon. But as clock frequencies started moving into the gigahertz range, the designers found that the package could become one of the elements that limited the performance of an IC. This new focus played a role for us at Xilinx, when we designed our next-generation, multiprocessor FPGA platform family and products.

When our design group started planning the design project for our new product platform FPGA project, we had to consider the ever-increasing clock-frequency design issue. Advances in transistor shrink also shifted the interconnect challenge from silicon to the package. Today, before we even conceive of an IC, we must make decisions about the package we are going to use.

Respinning our design to fix unforeseen performance problems would be a costly proposition, given that the new product had up to four microprocessor blocks and as many as 24 transceivers. We needed to know what we would get at tapeout and not at fab-out. To achieve this goal, we needed to optimize the IC and package to meet our parameters: cost, performance and time- to-market.

Designing a flip-chip package with up to 1,200 pins for the new product entailed multiple constraints. Thus, we developed a "characterization-driven design flow" with a software-based modeling technology that we could trust. A key requirement was that we could back up the design with measurement data that provided correlation with the software models.

Eye openings

The voltage and timing margins at the receiver ultimately determined how well our chip would perform in an actual system. The circuit and package were tuned together such that the receiver circuit would see maximum eye openings. In some designs the high-impedance bond wires or package traces near the die would offset the input capacitance of ESD structures and receivers, and thus help open up the eyes.

We discovered several traits: A clean eye at the package pin does not mean a clean eye at the receiver circuit. Also, the driver circuit needs to be tuned such that the output waveform at the package pin, instead of silicon pad, will have proper voltage swing, rise/fall time and duty cycle. We found that good package models were crucial and a dedicated package simulation software, such as PakSi-E from Optimal Corp., became one of the most important tools for us. With it, we were able to accurately model the 3-D geometry, even for a folded substrate in a flex-pc-board environment.

We chose a high-layer-count, flip-chip package to support the multigigabit transceivers in our design, which we also prototyped for our initial product sampling. We created the electrical models with PakSi-E and Sidea. These models indicated that, even though the package could deliver the required performance, we could make several improvements to the design. We implemented a new design and again confirmed its performance using both PakSi-E simulation and measurements.

Clearly, we found that designing at 130 nanometers and planning to design below that requires new design outlooks and methods. For all subsequent high-end designs, our design group at Xilinx will co-design and optimize the silicon and package in all our subsequent projects. With the availability of package-modeling and simulation tools, the package design can become an integral facet of whole-chip design.

Paul Y.F. Wu is packaging design manager and Soon Chee is advanced-package development manager at Xilinx Inc. (San Jose, Calif.). Co-author Ching-Chao Huang is chief technical officer at Optimal Corp. (San Jose).

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