Unified data model brings signal integrity

Unified data model brings signal integrity
Electronic design automation has evolved over the past 20 years as isolated activities for each piece of a design. It has been common practice to separate the electrical design and analysis from the physical implementation domains at both the IC and package/module and printed-circuit-board levels. EDA vendors have developed closed methodologies and tool sets for different design phases, requiring manual handoffs and multiple iteration loops that can result in costly errors and delays.

However, the complexity of today's new technologies bridges these traditional domains and renders traditional design methods inadequate in terms of accuracy, efficiency and cost. An entirely new EDA approach is required in order to ensure complete design closure between IC, package, module and PCB design phases.

Designing a high-frequency wireless product typically involves several major design domains or phases:

-Architecture and system design: The wireless product is modeled and verified at the system level using architectural or behavioral components. The overall functionality and performance of the system, including data throughput, channel interference and power consumption, is simulated, refined and verified. Individual component requirements and specifications are then defined and passed to the circuit-design phase. A decision on the final product packaging, such as a multichip module on a laminated substrate or on a pc board, is typically determined in this phase.

- Circuit design: The individual components are designed at the transistor level (for custom digital, analog and RF circuits) or at the gate level (for digital control circuits), then simulated and verified. Ideally, the system-level specifications should be used as testbenches to verify the component performance compared with the overall system requirements.

-IC physical implementation: The component circuits are physically laid out in one or more ICs depending on the original system requirements and chosen architecture. The layouts, including device and interconnect parasitics, are then physically extracted and verified to ensure final performance and that they can be manufactured. Ideally, the parasitic effects from the physical IC package--that is, from lead pins, bond wires and on-chip bond pads--should be considered at this time.

-Module and/or pc board physical implementation: The ICs are placed and interconnected in the module package or board or both with other off-chip passive components, such as resistors, capacitors and inductors. Ideally, the entire module or board or both should be reverified with the module/PCB interconnects to verify the final system performance. Critical signal paths that go from internal IC circuitry and through IC bond pads, the bond wires or lead traces and the package pins and onto the module or board traces should be extracted, modeled, simulated and verified to ensure that there are no performance bottlenecks imposed by these paths on the overall system.

To illustrate the complexity of the signal-integrity concern, take an 802.11a wireless LAN transceiver module design.

The complete 802.11a transceiver design has several major sections:-The transmitter circuit chain includes the orthogonal frequency division multiplexing (OFDM) transmit block, the upconverter mixer, a local oscillator with phase noise characteristics and a transmit power amplifier. -The receiver circuit includes the low-noise receive amplifier, the downconverter mixer, the signal scaler, the automatic-gain-control circuit, the OFDM receive block and the disassembler. -The system is excited with complete modulation signals at 54 megabits per second and the 64-QAM signal generator fully complied with the 802.11a specifications. -Channel loss is also modeled.

The entire 802.11a transceiver RF chain, including the channel and channel loss, is first modeled at the system level and simulated. Each circuit block is then designed and simulated individually. Next, verified circuit blocks are physically laid out, with individual devices placed and interconnects routed. The entire RFIC is then assembled from the layout blocks and verified. Finally, the module design is completed with the RFIC and a number of off-chip passive components.

The challenge for high-performance product design teams today is that all these design phases are isolated by separate EDA design and analysis environments, incompatible databases and use tools and models that are not designed for gigahertz frequencies. Many high-frequency circuit impairments and signal integrity problems, such as delay, noise, distortion and impedance mismatch, are ignored when the signal paths cross the chip, package and module-board boundaries. The separate EDA environments and databases prevent designers from analyzing signal integrity early in the design cycle, where it is most critical.

The physical structure of a signal trace starts from a chip bond pad, travels through the bond wire, onto the metal traces inside the package, through the package ball grid and onto the module surface. The signal continues through several interconnect traces on the module on different layers and finally ends back on another chip pin.

Because of inconsistent environments and poor modeling and extraction capabilities, it is difficult to effectively co-simulate and analyze the signal trace between the physical-implementation phases at the IC and module-board levels. In addition, the disconnect between the chip and package physical design tools and flows means more delays and rework due to poor comprehension of the interfaces. Inability to obtain complete design closure between the physical implementation phases may result in added iterations and costly product and market delays.

The factors that contribute to the difficulty of solving chip-in-package and in-module signal integrity problems include the design and analysis tool requirements at the chip, package and module implementation levels; current EDA data representations that describe the underlying physical structures; and process technologies that have to be supported. None of the mainstream EDA solutions were designed to support the diverse set of requirements.

A new and highly integrated chip-package-module EDA solution is needed to address the complex cross-domain signal-integrity matters that are inherent in the design of next-generation high-performance, high-frequency products. Even for a single chip-in-package, it is essential that this new EDA solution be designed from the ground up to comprehend all design domains.

To achieve optimum design closure, the solution should be built upon a unified data model and design environment encompassing all of these domains. The data model must be high-frequency aware, permitting accurate extraction and modeling of all design elements, including active and passive devices as well as interconnects at high frequency. The new solution must also be built on an open, standards-based software platform, enabling easy integration of the most capable, best-in-class tools to capture, synthesize, simulate, optimize, layout, extract and verify designs in all domains.

James Spoto is CEO and president and Tom Quan is vice president, product management, at Applied Wave Research Inc. (El Segundo, Calif.).

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