Materials make signal difference

System-on-chip (SoC) design has traditionally catered to an obsession with fine-geometry CMOS. Each process node-the shift from 0.18 to 0.13 microns and then to 90 nanometers-has meant that more functionality could be incorporated on chip. The smaller line widths allow CMOS transistors to function on lower voltages and to trigger on faster clocks. Such an obsession, however, wreaks havoc with analog and mixed-signal designs. With each process shrink, the signal-to-noise ratio declines, and linearity and dynamic range are lost. If analog and mixed analog-digital circuitry represents the means of launching signals into the real world, clearly something more is needed.

As In Focus contributor Frank Thiel of Legerity Inc. (Austin, Texas) points out, amplifiers are the building blocks of analog and mixed-signal design. It's a challenge to build a precision or wideband amp out of dozens (or even thousands) of clattering CMOS switches-especially those amps that must drive video cables, RF antennas, telephone twisted-pairs and precision data converters. Thus, this collection of contributed articles discusses specialized materials and processes for mixed-signal design.

Bipolar technology heads the list of processes most desired by the contributors. Unlike MOS transistors, bipolar devices allow current to flow in two directions: between emitter and collector, and vice versa. With their ability to control current flow, bipolar transistors make inherently better amps than CMOS transistors. A totem-pole configuration consisting of npn and pnp bipolar transistors, each driven by the same analog source, would create a "push-pull" effect-suitable muscle for driving motors, audio speaker coils or RF antennas.

Until recently, the problem with so-called complementary bipolar processes-that is, technology that would integrate npn and pnp devices on the same chip-is that the devices would be grossly mismatched. Unless the IC designer was prepared to devote a disproportionate amount of silicon area to the design of the pnp, its performance would never match that of the npn. The current drive of the pnp might approximate that of the npn, but not the transition frequency (ft). Thus, you'd have a "push-pull" amplifier with all pull and no push.

Consequently, you'll find the contributors to this article package-many of them working from company position papers-extolling their well-balanced complementary bipolar processes. James Karki of Texas Instruments Inc. (Dallas), for example, writes about complementary silicon germanium (SiGe), a blend of conventional BiCMOS with SiGe npn and pnp devices. The transition frequencies of both device types are in the 20-GHz region and are matched to within 1 GHz, although the npn still has higher gain.

Michael Maida of National Semiconductor Corp. (Santa Clara, Calif.) describes a complementary bipolar process with similar specifications. Without the benefits of SiGe, these transistors have transition frequencies in the 10-GHz region, though the npn and pnp are similarly matched to within 1 GHz.

Though lobbying high-voltage capabilities, Legerity's Frank Thiel also mentions the importance of matching npn and pnp devices. His company's bipolar devices have matched ft in the 1-GHz region. The difference is that Legerity's complementary bipolar devices-meant to withstand 150-volt surges-need not be as fast as those proposed by Texas Instruments and National. There is a noticeably inverse relationship between speed and drive capability: the higher the ft, the lower the drive capability, and vice versa. But these processes are meant to serve specific real-world applications: Legerity's high-voltage products are meant to interface telephone lines in central switching facilities and to effect 90-V ringing at the end of a 2,000-foot twisted-wire pair. National's bipolar devices are intended to support the CATV industry by driving video signals through 50- or 75-ohm coaxial cable. And TI's SiGe devices have signal acquisition for cellular base-stations written all over them.

You'll notice that dielectric isolation appears as a key concern of amplifier designers. Simply stated, the bipolar driver transistors perform at their best when there are no parasitics sucking away at their fringes. The kind of dielectric isolation the contributors tout is one that physically and electrically isolates the bipolar transistor from the substrate, often CMOS, that holds it. Some contributors will appear to criticize "junction isolation," primarily because it's leaky. Dielectric isolation-once implemented by an expensive wafer-lapping process-would so physically isolate the bipolar transistor that stray currents would have no place to go but to where the metal contact layers directed them. Actually, the kind of dielectric isolation described in the articles here, especially those implemented with BiCMOS processing, might be closer to a "new and improved" junction isolation. For the most part, it's a silicon-on-insulator (SOI) process.

In addition to the performance advantages of SOI, you should pay attention to the silicon area taken up by the complementary bipolar transistors. Because of the required p-well, the pnp transistor generally required a larger silicon area than the npn. In addition, as suggested, its construction and performance were sloppy.

A buried layer-a physical isolation layer, creating an artificial dielectric-not only improves the performance of the pnp but also reduces the silicon area required to build it. If you study the process cross-sectional diagrams these authors provide, you'll notice an interesting symmetry between npn and pnp devices-a symmetry that could not exist before the improvements in SOI technology. Thus, complementary bipolar technology can be molded as more than a standalone process for high-performance analog, but something that will support BiCMOS SoC integration as well.

This emphasis on bipolar processing does not displace the emphasis on CMOS or the push on designers to accomplish whatever they can in this workhorse technology. In his lobby here for RF CMOS-a 0.35-micron process licensed from the Taiwan Semiconductor Manufacturing Co.-Austriamicrosystems' Ron Vogel mentions that even the high-performance analog must be integrated with CMOS wafers in the typical foundry flow. Thus, a high-volume foundry like TSMC will provide technology road maps suggesting how high-voltage processes, BiCMOS and SiGe can be incorporated with conventional CMOS designs.

A footnote to TSMC's road map-and a central concern of William Boyd's article here-is a process called linear CMOS. CMOS transistors pop into saturation with little provocation. They are thus wonderful switching devices, they build very complex logic and memory circuits, but they introduce noise. Some manufacturers will suggest that linear CMOS devices smooth the transition between on and off states, making them less noisy and easier to bias as amplifiers. The larger emphasis is on implantable components-resistors and capacitors that support tuning and filter circuits. The process described by Boyd provides metal-insulator-metal capacitors and trimmable silicon-chromium resistors-components that add precision to analog signal-conditioning tasks in CMOS.

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