Three allies take on 90-nm verification

Three allies take on 90-nm verification
San Jose, Calif. - Three EDA verification tool vendors are announcing an ambitious plan to develop a unified verification flow and methodology to ease verification of system-on-chip designs targeted for 90-nanometer and 65-nm processes. Verisity Ltd., 0-In Design Automation Inc. and Novas Software Inc. will work together to create common data models among their respective tool sets.

Functional verification is acknowledged to be the most time-consuming task in IC development, accounting for as much as 70 percent of overall development time. That percentage is not likely to decrease as designs are implemented in more-advanced processes.

"High mask costs mean that people targeting 90 nm are going to put as much programmability and configurability as they can into their chips," said Steve Glaser, vice president of corporate marketing and business development at Verisity (Mountain View, Calif.). "It means that they can use the same silicon for multiple product lines." But verifying such a complex chip will be an enormous task.

So the three partners are creating common data models that will bridge their respective tool sets and areas of expertise: Verisity's testbench technology, 0-In's formal and assertion-checking tools, and Novas' hardware debug. The partners hope the common models will create a unified flow for verification process automation (VPA) that will sit atop a "verification infrastructure" of third-party simulators, accelerators and emulators. They are focusing initially on hardware verification but plan to address software down the road, likely through an expansion of the alliance.

"The idea of the collaboration is to automate all of the engineering-intensive tasks in the verification process," said Dave Kelf, vice president of marketing at Novas (San Jose). The companies hope their collaboration will shrink the time required to perform functional verification by a factor of 10.

VPA will allow a verification plan to be created that can be effectively distributed to various team members for system, chip- and unit/block-level verification. It is also intended to automate many of the tasks overseen by verification team members.

Verisity will define the top-down, spec-driven verification management process, extending from an executable verification and coverage metric plan to the composition of a multilevel environment for unit, chip and system verification.

0-In will define the implementation-centric design-for-verification flows, incorporating assertion-based and formal verification. Assertions will link the design with the specification and may span multiple levels of abstraction, the companies said. 0-In will provide two processes. The first will focus on verification hotspots that are verified with formal verification techniques. The second will address critical coverage points in a design that can be monitored with assertions in dynamic verification.

Novas will define the debug and failure analysis flows spanning the range of activities from signal to transaction levels. That will allow users to detect the root cause of bugs in the VPA flow, Kelf said.

The companies' common data models will allow their respective tool suites to work tightly together and to be viewed by users as a unified environment, said Richard Ho, cofounder and senior architect at 0-In Design (San Jose).

The companies said that common data models will enable each tool to work with the latest and most complete set of information. The models will ensure that VPA users are working from a common plan that specifies what needs to be verified. They will also ensure that the companies' tools work from the same servers and licenses and can access specific run data, statistics and log information.

The companies also want to ensure that the tools run from the same coverage models. They intend to have the tools work from actual coverage and trace results for verification runs, whether simulation-based or formally verified. And they want the tools to share information about failed runs and to share relations among data items.

They hope to have the major issues ironed out in time for the 41st Design Automation Conference, to be held June 7-11 in San Diego.

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