News & Analysis

I/O choices get tougher

Rick Merritt

11/7/2003 2:23 PM EST

I/O choices get tougher

Just when you thought it was safe to make an I/O decision, new interconnects keep popping up and old ones keep staking out fresh territory. Multigigabit interconnects are posing new implementation challenges at the board and systems levels for everything from next-generation PCs to network switches.

Besides the imminent arrival of Serial ATA, Serial Attached SCSI, 4-Gbit Fibre Channel, PCI-X 2.0 and PCI Express interconnects that will affect the storage sector, recent interconnect announcements have focused on dataplane packet processing for networking gear.

The RapidIO group unveiled new flow-control mechanisms in September. Days later, the HyperTransport Consortium rolled out a native packet-handling capability. And at October's Communications Design Conference, Intel Corp. announced the 1.0 spec for its Advanced Switching for PCI Express, and six companies formed an ad hoc group to back it.

Days after that, Xilinx Inc. and four partners rolled out their Universal 10-Gbit physical-layer initiative defining a 10-Gbit serdes based on a binary approach. Lurking in the bushes, a competing Multi-Level Signaling Alliance is coalescing to promote a PAM4 approach. Both face daunting issues characterizing physical channels for 10-Gbit backplanes.

The backplane work could still be well ahead of real OEM demand. For example, while most of the backplanes in Cisco Systems Inc.'s products now run at 3.125 Gbits/second, the company hits 40-Gbit rates to some line cards by aggregating the signals. Moving to a native 10-Gbit backplane is less important than getting layer-three switching silicon up to 10 Gbits and providing thermal management for high-end systems, said one top Cisco engineer manager.

"Today, I can build a backplane with more bandwidth than I can cool. That's just a reality," said Bill Jennings of Cisco's networking group.

Here, we provide guidance for engineers taking their first crack at implementing RapidIO and PCI Express. Three articles provide advice about how to characterize 6-Gbit+ backplanes. Others sort through the tangled array of I/O options. We hope these offerings speed you along toward the multigigabit future.





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