News & Analysis
Synchronous vs. Asynchronous
6/6/2003 4:20 PM EDT
Synchronous vs. Asynchronous
Clockless IC designs are ready to compete
Time to dispel clockless logic design myths
Breaking the EDA barrier in async design
Clock domain modeling is essential in high density SoC design
Does asynchronous logic design really have a future?
Asychronous design gets a second look
As system-on-chip (SoC) designs grow larger, designers must grapple with serious global
timing problems, the effect of wire loading and timing delays and the performance hit
associated with supporting on-chip communications between different clock domains.
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