News & Analysis
EDA/Design for Test
3/3/2003 11:15 AM EST
EDA/Design for Test
Circuit and Platform Design Challenges in Technologies beyond 90nm
Fault coverage founders on speed
Bandwidth match avoids I/O snarl
Creating Value Through Test
Pre-configured DFT structures can simplify ASIC design, verification
DFT: A systems technology for system chips
Interoperability testing is critical for broadband deployments
Shifting from functional to structured techniques improves test quality
Moving DFT to RTL overcomes test vector issues
Linking synthesis with DFT key for network switch ICs
Analog circuits need more than just DFT methods
DATE attendees ponder 90nm test strategies
The enormous capacity of system-on-chip devices to integrate
diverse functions makes wide-ranging design ideas necessary,
and among the new functions showing up on systems-on-chip
are test-and-measurement subblocks.
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