Designers ponder unified data transport era

Designers of multigigabit transceiver and serializer/deserializer chips have argued for nearly a decade that, as backplanes, fabrics and in-system interconnects reach speeds of 2 to 10 Gbits/second, the design problems will be similar whether the interconnect goal is interchip links, unified backplanes or board-to-board I/O. In fact, some serial-link tasks will be common to interconnects that range outside the box, into multiserver clusters and grids.

That theoretical day has arrived. While the proponents of specialized high-speed interconnects like HyperTransport, RapidIO and PCI Express insist their architectures serve complementary purposes, all of them share common design issues as they shift from parallel to serial implementations and as they find overlapping applications in linking to larger-radius interconnects like USB, 1394 and Infiniband. Some physical-layer design concepts also can be borrowed for the nascent efforts to define common backplane specs beyond 2.5 Gbits/s, like the new High Speed Backplane Initiative.

Those concerns are no longer relegated to in-system design of servers. They are directly relevant to telecommunication and data communication equipment design in at least two aspects: First, the primary applications for new interconnects will be communication equipment like routers and multiservice switches, as groups like the PCI Industrial Computer Manufacturers Group realize. Second, many point-to-point links also can be implemented as switch fabrics, creating an interesting spectrum of direct serial interconnect evolving to meshed fabrics to create switched racks of expandable telecom equipment.

The worthy goal of adding higher-layer protocol support to AdvancedTCA raises an interesting issue in serial interconnect, which StarGen Inc. executives say they have seen coming for several quarters in the StarFabric environment: Because of Ethernet's ubiquity, some OEMs have talked of using Ethernet framing as a backplane, in and of itself. But proponents of all the new serial interconnects and backplanes are united in seeing Ethernet as carrying a Layer 2 (data link layer) overhead, which is inappropriate for most high-speed interconnect functions.

Hence, just as network processor vendors often argue for strict segmentation between control plane and data plane, the serial interconnect camps are pushing for a strict segmentation between physical-layer functions and data link functions. There's nothing wrong with Ethernet as a data link technology for local-area network or wide-area network and even storage-area network applications, but backers of HyperTransport, RIO and PCI Express are united in saying that Layer 2 should be reserved for true data packet translation, not used as a fast way to move data point-to-point.

Contributors to this week's In Focus look at a variety of issues in designing high-speed interconnects at 2.5 Gbits/s and beyond. Some look at physical-layer chip design, some concentrate on implications to the system of adding high-speed I/O to the line card. Applications can blur the differences among backplanes, switch fabrics and point-to-point links, as the articles will indicate.

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