News & Analysis
High-Speed Design
10/7/2002 10:30 AM EDT
High-Speed Design
Data interface key to future apps
Building a 6.25-Gbit/s backplane
LVDS ups A/D converter data rates
Buffers minimize jitter in clock distribution, differential signal lines
Active channels replace passive interconnects to meet high-speed demands
Topologies crucial for new backplane designs, architectures
Standards are key to optimizing high-speed data bus communications
Interactive tools enable "what if" experiments with high-speed clocks
Designers weigh in on the 6.25-Gbit/s move
While "gigahertz processors" are using 400-MHz external clocks with internal multipliers to obtain 1.2- or 1.6-GHz clock rates, that doesn't mean system designers aren't experiencing problems with data pumping.
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