Interactive tools enable "what if" experiments with high-speed clocks

Interactive tools enable "what if" experiments with high-speed clocks
Today's designs feature more complex components, denser circuitry, increased clock speeds, faster rise times, and lower operating voltages. And, these features create signal integrity issues that many engineers have to solve with an increasingly shrinking design cycle.

Engineers need the capability to explore signal integrity within designs by experimenting with device technologies, connection topologies, board layer stack-up, and termination strategies. Printed circuit board design tools must include the ability to set placement and routing constraints and perform post layout verification.

Consider the typical design flow: The design process begins with a designer chooses a representative driver/receiver pair for exploring the difference in performance for a variety of layout topologies. Once a topology is chosen, the designer can explore the effects of layer stack-ups, terminations, and crosstalk.

The first step in a study of high-speed effects is to start by picking a representative driver/receiver technology family. Advanced Low Voltage (ALVC) CMOS is a good technology to examine for clock signal design because of it's fast rise time and low operating voltage. Low voltages, on the other hand, can cause several signal integrity issues.

A choice for a tool to examine these effects is one that employs IBIS models to simulate driver/receiver behavior. The ALVC driver model has rise and fall times in the range of 1 - 2 nanoseconds, with an output resistance of 7 - 12 ohms, and output capacitance of 5 picofarads. The receiver has an input impedance of 1 Giga-ohm and an input capacitance of 10 picofarads.

Let's assume a scenario with a microstrip trace model on an outside layer of a pc board using FR4 with a relative dielectric constant of approximately 4.3, a length of 100mm, propagation velocity 0.18 mm/picosecond and 90-ohm impedance. The simulation under this initial assumption has a rise of 1.5 nanoseconds and overshoot of 0.73 V with a settling time of 4.7 nanoseconds at the receiver.

The results imply that a driver/receiver pair using ALVC technology connected by a 100mm trace on the top or bottom of an average pc board can have significant ringing and therefore significant signal integrity issues.

Once the driver and receiver have been selected, the effect of distributing the clock signal to multiple devices can be addressed and modeled. This is modeled by adding several more receivers with the same receiver ALVC IBIS input model to the existing driver/receiver pair.

The analysis tool user has a variety of connection topologies to choose from including a "User Defined" topology. In this case, the engineer simply creates a scenario, connects symbols representing drivers, receivers, and transmission lines in the "Topology Editor" of the tool, and then executes the simulation.

In this instance, we will explore Daisy Chain and Remote Star for comparison purposes using Zuken's interactive signal integrity tool, the Hot-Stage Scenario. Initially, the review of the results for a driver with eight receivers connected in a Daisy Chain topology with the same microstrip trace model is the first example. Each receiver is connected by a 100 mm trace. The simulation of this configuration would show the expected waveforms at each of the receiver inputs. Using a Daisy Chain topology in this manner adds approximately 6.6 nanosecond s of skew between the output of the driver and the input of the eighth receiver. Overshoot and distortion due to reflections are observed in the waveforms.

Alternately, a scenario using a Remote Star connection provides equal trace length from the driver to each of the eight receivers, eliminating skew. The rise time increases to 2.6 nanoseconds and the overshoot and settling time significantly improve.

So far, we have been able to quickly experiment with several different topologies and view the resulting waveforms from simulations using IBIS models representing the clock driver and its intended receivers. We can continue with pre-schematic exploration by using the Remote Star topology example for clock signal distribution and proceed with reviewing choices for layer stack-up.

Essentially, the Configuration Editor shows a graphic representation of the trace configuration, its material, layer thickness, and dielectrics. This editor allows the engineer to change the trace model, re-simulate, and compare waveforms. The Configuration Editor has a built in field solver to calculate the unit values for the RLGC matrix used in the Lossy Transmission Line model.

The configuration to a stripline with a trace width of 0.1mm situated between two power planes using FR4 material with a thickness of 0.2 mm, yields an impedance of approximately 62 ohms and propagation velocity of 0.15 mm/picosecond. The width of the trace can easily be increased to reduce the impedance. A trace width of 0.2 mm has an impedance of approximately 45 ohms.

Re-simulating the scenario with the trace as a stripline results in approximately the same rise time as in the stripline scenario. However, there is a notable improvement in overshoot and settling time. Overshoot was reduced by 50 mV and settling time improved by over 1 nanosample. Make the assumption that this is a reasonable trace configuration and then add a termination to the scenario.

A termination strategy
Using the Topology Editor, terminations can be added to the scenario and re-simulated. The Simulator allows the engineer to run a parameter sweep on a termination and plot its value against waveform characteristics including rise time, overshoot, and settling time. By running a parameter sweep for a series termination, and placing a small resistor close to the driver in series with the receivers.

After reviewing the swept parameter plots, a 22-ohm resistor appears to be a good choice for this scenario. Rise time was lengthened to 3.7 nanoseconds, overshoot reduced to 170 mV and settling time was eliminated.

The next task is to determine the effect of crosstalk on two traces 0.1 mm wide, 100mm in length, separated by one trace width and located on an inner layer between two power/ground planes.

In this case, it is assumed that the return paths are good and directly underneath each signal trace. Trace widths, separation, and dielectric thickness are among the parameters that can be varied in the Configuration Editor. Running a simulation for a scenario with this configuration shows 436 mV superimposed on the "Victim Trace."

Increasing the distance between the Aggressor trace and Victim trace to just two trace widths dramatically reduces the voltage introduced into the Victim trace.

It is imperative that engineers know up front if there are signal integrity issues with their designs. Decisions can be made in the pre-schematic phase of the design process that can insure a successful product. Thereby, allowing the engineer the ability to spend his time more productively, designing product features rather than sifting through reams of tabular data isolating traces to determine if signal integrity is a problem.

Let the tool to do the math and present the results to the engineer in a form that is instantly recognizable. The engineer can see the familiar waveforms and then pass the knowledge gained from these scenarios directly to the pc board layout phase for component placement and auto routing through constraint management.

By using interactive signal integrity tools engineers now have the capability to evaluate and mitigate signal integrity problems before the printed circuit board is fabricated.