SOI CMOS requires complex modeling

Partially depleted silicon-on-insulator CMOS has become popular today in producing high-speed microprocessors. The speed increase results from several known advantages, such as the reduction of the drain and source capacitances and, essentially, from the threshold voltage lowering due to the floating-body effect.

In partially depleted SOI, the internal substrate of the MOS transistors, called the body, is floating. Its potential depends on the different charges injected into or extracted from the body region. Charges are injected by several mechanisms: the impact ionization current when the transistor operates in saturation, the GIDL current when the transistor operates in accumulation and the gate-tunneling current, which cannot be neglected anymore in advanced SOI CMOS technologies (gate oxide thickness below 3 nanometers).

The charges are extracted from the body through a recombination process in the body-source and body-drain junctions. The body of the SOI transistor is also capacitively coupled to each of the other terminals of the transistor, which means that the body potential will increase every time the gate, drain or source voltage rapidly increases, and will decrease every time these voltages decrease. The body potential will then vary during any switching event. Most of the time, the body of the partially depleted SOI transistor is forward-biased, resulting in a decrease of the threshold voltage and an increase of the drive current, which explains the higher speed.

The counterpart of the speed advantage is more complexity at the circuit design level. The body potential settles at any time to a value that depends on the previous bias conditions applied to the transistor. At the logic-gate level, this translates in a variability of the propagation delay through the gate-which is referred to as the history effect. Since the first switching of a given gate may be faster than the second one, a chain of several of these gates will then exhibit a pulse-stretching effect. The signal will propagate faster through the chain at the first switching and slower at the second switching. The pulse-stretching effect will vanish if the gate is switched permanently.

This history effect is generally seen as a nightmare from the designer's viewpoint. Many designs are achieved by logic synthesis using a digital library. The standard-cell library is a large set of digital gates containing all the necessary gates for designing a digital circuit. The library must contain all the information characterizing the gates: Boolean operation, speed, power consumption. In the case of bulk-CMOS libraries, each gate is characterized considering the varia-tion of several parameters-for example, the input rise or fall time, output capacitive load, power-supply voltage variation, temperature variation and technology variations (gate length dispersion, for instance). A variation in any of these parameters leads to a variation of logic-gate propagation delay.

The design teams are used to a well-established design flow based on the library. Therefore it is crucial to maintain the compatibility with this flow when designing with partially depleted SOI CMOS. The history effect must be accounted for in the electrical characterization (which is achieved by Spice simulation) of the library to yield an accurate timing analysis without modification of the library format.

The best solution is to treat the history effect as an additional variation of the propagation delay and include it in the library file, combining it with the other variations (temperature, power-supply voltage, process). The delay variations due to the history effect must then be properly evaluated for every gate of the library, using a sophisticated electrical-characterization method. The history effect depends on many parameters, such as the input rise/fall time, the load capacitance, the sizing of the gate and the switching configuration, which becomes more complex as the gate grows more complex with the number of input combinations increasing. It also strongly depends on the features of the SOI CMOS technology.