Check the EDA barometer

"If you don't like the weather, wait a minute." These days, Mark Twain's adage about meteorological forecasting in New England applies to predicting the business environment in electronic design automation. Indeed, in EDA, we need a weather map-a high-level view-to drive an accurate forecast. I believe an examination of the fundamentals of our business brightens the outlook considerably.

Moore's Law still holds true, meaning that every 18 months the number of transistors contained on an average chip doubles. That in turn means that the total number of gates being designed increases by about 50 percent every year, even in these tougher economic times. This makes sense because a much larger device can accommodate the functionality that would previously have been included on two or more chips, accounting for the somewhat counterintuitive decrease in design starts.

The effect of increased gates per chip does not stop here. An important boundary has been crossed in that an embedded processor may now be included on a device, transforming the design and verification process. Dataquest has predicted a rise in embedded-processor usage of 8 percent per year for the next few years, and already more than 50 percent of the devices created today contain such a component.

As they consider their next design, project teams must trade off extreme-complexity issues with time-to-market constraints, compounding design and verification methodology pressures. The result is an opportunity for EDA companies to address these greater requirements.

Verification now consumes 60 percent or more of the overall project cycle. Timing issues cause multiple, unexpected device respins. Unexplored system requirements manifest themselves during device prototyping or emulation.

Design complexity has begun to drive the next discontinuity in EDA, with new mechanisms to tackle the problems appearing at companies that are willing to invest in the future.

An area worthy of close attention is the language of the next decade's design flow. New modeling languages that cover both design and verification will be key components of future methodologies and drivers of important technologies. They will extend into the reaches of system exploration while enabling implementation-detail descriptions and providing evolutionary paths to new design paradigms.

Standardization efforts such as Accellera's SystemVerilog and its superset, Co-Design Automation's Superlog, are blazing a path for new technologies to combat design and verification problems. These developments will provide a framework in which new tools can effectively operate.