LSI Logic taps TSMC for fast track to 90-nm technology

Now that foundries have become a powerful force in the semiconductor industry, it's tempting to think that many integrated device manufacturers risk becoming irrelevant. But while the economics of chip making have forced many of the larger players to give up their puritanical devotion to fabs and process technology, their ties to manufacturing aren't about to come undone.

Consider LSI Logic Corp. The world's third-largest ASIC manufacturer this week will announce that its next-generation ASICs will be based on Taiwan Semiconductor Manufacturing Co.'s newly minted 90-nm process technology. Although LSI Logic had previously shared elements of 0.13-micron process with TSMC, shifting a portion of its production to a foundry is a first for the company.

"It's a recognition of the cost to develop a new process technology; it's difficult for a $2 billion company or even a larger company to shoulder [that cost burden] alone," said Jordan Selburn, principal analyst at iSuppli Corp. (San Jose, Calif.). "Second, silicon per se is becoming less a differentiating feature. There's less to gain by keeping your own private recipe."

Others that have struck similar "alignment" deals with TSMC are Motorola, Philips, STMicroelectronics and NEC. And TSMC says that at least six more IDMs whose names have not been disclosed have done the same.

Even so, LSI Logic said it will have to stay sharply focused on process technology in order to reconcile its design methodology with the idiosyncrasies of the silicon.

By using TSMC, LSI Logic said it will be able to take its first 90-nm designs by year's end, just as 0.13-micron designs begin to ramp up. Such an aggressive technology shift would have been hard to imagine had LSI Logic tried to go it alone.

NRE on the rise

Indeed, few customers can afford to move to the latest-generation process technology because of ever-increasing nonrecurring engineering costs. The mask set alone could cost more than $1 million or more at the 90-nm node, which some say could draw more customers to existing 0.18-micron and 0.13-micron design rules.

That makes it hard for a company like LSI Logic to roll out a process technology early. Foundries, on the other hand, can cull many more customers earlier in the technology cycle as a way to offset the development costs, said Ronnie Vasishta, vice president of technical marketing for LSI Logic (Milpitas, Calif.). Under the company's plan, TSMC will handle its early production, throughout 2003 and early 2004.

Does this mean LSI Logic has become a glorified design services company? Hardly. Many elements of design, manufacturing and packaging have become so intertwined that it often takes one company to see the design through to the final product.

"They take responsibility that the parts will meet functions and timing for signoff. That's the chasm between the ASIC vendor and a design services firm," Selburn said.

Further, LSI Logic will outsource only about one-third of its production capacity. When volume production starts to ramp in 2004, LSI will transfer the 90-nm process to its own fab in Gresham, Ore. — a move that should allay customer concerns about the possibility of getting bumped in the queue at a foundry.

Moreover, LSI Logic intends to make its money by shipping devices in volume, not by selling its design services, Vasishta said.

And it will continue to take ownership of the mask sets, although that question could be open to negotiation for some of its largest customers, according to iSuppli's Selburn.

By shifting to TSMC's design rules, electrical parameters and transistor characteristics, LSI Logic can devote more of its resources to such pursuits as development of standard-cell libraries. The company's high-density single-port SRAM cell size, for example, will be roughly 1 square micron, about the same size as Intel Corp.'s recently announced SRAM cell size for the same process technology node. LSI Logic will also offer multibank RAM that is 25 percent larger but that has faster setup and access times.

Differentiators retained

To serve communications customers, the company has readied various I/Os, including low-voltage differential signaling, stub-series terminated logic, PCI and double-data-rate interfaces. It expects to introduce several high-speed serial I/Os early next year.

"The process technology is plenty important, but it's the execution and putting different blocks together that is the real differentiator," Vasishta said.

Another area where it can add value is packaging. The company has developed its own six-layer organic-substrate flip-chip at the high end, as well as a lower-cost, four-layer package. "For some chips, over half the cost is the package," Vasishta said.

LSI Logic will continue to employ third-party CAD tools as often as it can, but will work to characterize the libraries for the tools. In some cases, it has developed its own CAD software. For example, the company uses Synopsys Inc.'s PrimeTime for static timing analysis but uses an internally built tool for delay calculation. The company also uses Avanti Corp.'s Apollo but has added its own placement-optimization and other placement and routing features.

The design methodology becomes more rigorous at 90 nm — a reflection of how sensitive the silicon is becoming to design. There are now seven distinct design signoff points in the design flow, allowing little room for last-minute design changes that could trip up a GDS2 file. "Before, customers would often ask us to just push something through. Today, it's just not feasible," said Jeff Vanderlip, director of ASIC technical marketing for LSI Logic.

In some ways, LSI Logic and other IDMs will act as R&D arms for TSMC as they work to mitigate the process problems that worsen at 90 nm, including crosstalk, inductance, leakage current, voltage droop and variations in metal resistance. LSI Logic will continue to conduct research on low-k intermetal dielectrics and to share its developments with its foundry partner, Vasishta said.

"You have to be a silicon provider to design with 90 nanometers this year, just because of the interaction of the silicon with the overall design flow," he said.