AMI tweaks gate array for FPGA conversions

SAN MATEO, Calif. — ASIC-based gate array vendors have for years been easy targets for makers of field-programmable gate arrays. But AMI Semiconductor wants to prove that gate array vendors can learn to adapt, and may even be able to turn FPGA vendors into unwitting allies.

This week, the Pocatello, Idaho-based ASIC vendor will unveil what it calls a hybrid gate array, a technology AMI claims will slash the time it takes to spin a prototype while lowering manufacturing and nonrecurring-engineering (NRE) costs. Moreover, the company has designed the new ASIC platform as a drop-in replacement for Xilinx Inc.'s Virtex-E and Altera Corp.'s Apex-E 1.8-volt FPGAs.

The so-called XpressArray platform is AMI's latest attempt to woo designers who like the convenience of FPGAs but find it hard to persuade their purchasing departments to buy these pricey devices in bulk when it comes time to ship systems in volume.

AMI, which offers both gate array and standard-cell ASIC services, has for years been turning the crank on FPGA-to-ASIC conversions, which can be a messy and tedious process, especially when trying to guarantee timing specs. For that reason, many FPGA and ASIC vendors have shied away from doing these conversions in-house, with Altera being a notable exception.

Expanding on that theme, AMI has tweaked its gate array technology so that it uses an array of low-level macros rather than the traditional sea of gates. AMI says these macros — consisting of various NAND gates, converters, muxes and configurable memories — require much less interconnect and are thus more area-efficient than the sea-of-gates variety, reducing die size. Performance, meanwhile, is comparable to that of a standard-cell ASIC, the company said.

At the 0.18-micron technology node, AMI claims the gate density of XpressArray comes close to that of a worst-case cell-based design, but it's an order of magnitude better than FPGA density. XpressArray boasts 41,000 ASIC gates per millimeter squared, while a standard-cell design at the same 0.18-micron process node would be somewhere between 45,000 and 90,000 gates/mm². Many designers would find little advantage in moving to a much higher-density cell-based design, aside from some marginal improvement in power density, due to die size limits imposed by the bond pads, said Vince Hopkin, vice president of AMI's digital ASIC division.

Gate density really shines when compared with an FPGA, which AMI estimates at 3,000 gates/mm² at 0.18 micron. Moreover, XpressArray is about two-thirds denser than programmable-logic devices converted to ASICs through Altera's HardCopy program, Hopkin said.

AMI's initial offering consists of eight devices ranging in density from 44,000 to 2.6 million ASIC gates. The device family includes up to 200 million internal registers and between 31 kbits and 1.4 Mbits of embedded memory. The parts have a system clock of 250 MHz and local speeds of 350 MHz.

To address the diversity of interface standards that have burst onto the scene, the I/O can be configured to support standards such as PCI-X, HSTL, SSTL, GTL and 622-Mbit/second low-voltage differential signaling. The I/O can tolerate voltages of 1.8, 2.5, 3.3 and 5 V.

The array also contains clock-management circuitry, up to 12 digital delay-locked loops and four phase-locked loops. Scan-test logic cells are included to facilitate "virtually 100 percent" fault coverage, Hopkin said.

AMI touts reduced design cycle time and lower development costs as two major advantages to using these predefined macros over the sea-of-gates approach. The company claims it can take register-transfer-level code or an FPGA netlist and have a prototype in customers' hands in six weeks while keeping NRE costs between $50,000 and $200,000 — well below the going rate for 0.18-micron standard-cell designs. Unit pricing can be anywhere from $6 to $200, and the company's volume requirements range from 1,000 to 1 million parts per year.

AMI said it keeps NRE costs low by using Taiwan Semiconductor Manufacturing Co. to fabricate wafers up to the second metal layer. The unfinished wafers can be stocked until AMI is ready to customize the final three or four mask layers at its own fabs. These final steps require only six reticles, Hopkin commented. "We can do it in four weeks and turn a chip in six weeks. The volume can be high, but we also support medium-volume business."

Another advantage is that AMI can use TSMC for the critical mask steps that require the most aggressive design rules, and then use looser design rules for the final customization. This will allow AMI to hold off buying the most expensive, cutting-edge manufacturing tools for its own fabs.

Going forward, XpressArray will replace AMI's traditional gate array offering, which stops at 0.35-micron design rules.

AMI will continue to offer standard-cell methodology below 0.35 micron.