Fabless ASIC supplier unruffled by downturn, exec says

Less than two years after the semiconductor industry veteran officially opened eSilicon Corp. for business, chief executive officer Harding claims to have garnered 10 design wins and expects to start shipping its first chips in volume next quarter.

Among eSilicon's first designs are a special delay-locked loop circuit for a digital camera designed for Eastman Kodak; an MP3 encoder/decoder for PortalPlayer; a home gateway device designed for 2Wire; and a one-million-gate device for an undisclosed set-top maker.

These projects won't generate significant revenue until the first chips start coming out of eSilicon's foundry, and Harding expects the design wins will eventually generate revenues in the "low tens of millions," but the company isn't quite ready to cut the venture capital umbilical chord.

The design wins are endorsements that show eSilicon can give its bigger rivals a run for their money, Harding said. They also show that the young company can be choosy even while the chip market remains bleak.

"We no-bid more deals than we bid," Harding said. "For every five, we'll quote one. And out of those, we win about a third."

Next year, eSilicon expects to make a shift from mostly digital designs to more sophisticated mixed-signal and system-on-chip designs, which Harding expects will help boost revenues to $100 million and then $200 million by 2004.

"By this time next year, we expect to design anything that anybody asks for," Harding said. "We don't lack any of the elements of bleeding edge. We just elected, as a young company, not to engage with too many designs at the bleeding edge."

eSilicon's infancy belies the experience of its management team, many of whom have more than 20 years of industry experience. Before founding eSilicon in 1999, Harding served as president and chief executive of Cadence Design Systems Inc., which he left after a management shakeup earlier that year. Chief operating officer Dennis Hollenbeck was vice president and general manager of Quantum Corp.'s high-end storage division, where he oversaw ASIC development. Most recently, eSilicon hired Mike Jacobs, former senior vice president of worldwide sales for Altera Corp., to run the company's sales organization and build up its roster of outside reps.

In the simplest terms, eSilicon can be categorized as another fabless chip startup that has taken advantage of dedicated chip foundries in Taiwan. The difference is that eSilicon is designing chips for other companies — a task normally assigned to self-contained chip companies with revenues in the billions, such as IBM Microelectronics, LSI Logic and NEC.

Harding doesn't consider eSilicon a design services company because it engages with customers at every point in the design cycle and assumes the manufacturing risk, right down to the delivery of packaged, tested chips. It reaches out to third-party EDA tool suppliers, manufacturers, packaging and test companies. Its sole foundry in Taiwan Semiconductor Manufacturing Co., but it has multiple sources for design tools, packaging and test.

Because it relies on TSMC to manufacture chips, eSilicon pays about twice as much for wafers as an ASIC company with its own fabs. Those expenses are made up by having virtually no depreciation cost and little R&D spending, Harding said. And that translates into higher operating profits than traditional ASIC suppliers, he said. "We have virtually no fixed costs. Our revenue might dip but we're never going to have a fab that we have to equip or staff," he said.

As further proof that the fabless ASIC model works, Harding pointed to recent announcements suggesting that even fab-owning integrated device manufacturers (IDMs) are getting into the act. Last September, for example, Intel Corp. formally announced its fabless ASIC division. Just five months prior to that, LSI Logic Corp. said it would collaborate on 0.13-micron technology with TSMC, and the company has stated that it will outsource more of its production foundries. Most recently, AMI Semiconductor said it would use TSMC's manufacturing process for the first two layers of its latest macrocell-based ASIC platform.

To Harding, these are not isolated events. "We're at a turning point where the traditional ASIC company is being asked to make custom chips they can't afford to make on an ongoing basis," he said.