Designing a low -power hard disk controller for converging products

Designing a low -power hard disk controller for converging products
A wide variety of devices, from Internet appliances and personal digital assistants to cellular phones, are in the process of merging functions. For example, cell phones are transforming into Internet screen phones, with screens and keyboards that can support e-mail and Web browsing as well as full audio, video and Internet communications. Central to this merging of different functions are miniature hard drives, which serve as temporary data storage.

The next generation of TV and set-top boxes will be all-digital television sets with high-definition picture quality. They will use hard-disk drives and will be capable of storing and playing up to 1,000 programs and movies. The TVs will be able to record the programs independently, and will contain many more options for user interactivity and personalization of the received content.

The evolution of data bandwidth from current Global System for Mobile Communications and code-division multiple access networks to third-generation cellular networks will support a true mass market of mobile multimedia applications. These examples demonstrate the importance of having an advanced hard-drive control suitable for portable and low-power environments.

These factors stimulated LDIC's engineers to look at a single-chip solution that would provide very low power with maximum data rates. The resulting design, the single-chip LD8010 Hard Disk Drive Electronics, is designed for 2.5-inch, 1.8-inch and 1-inch drives. It was fabricated in modified 0.25-micron BiCMOS technology to operate with a 3.3-volt power supply.

The system-level chip integrates the read/write channel, ATA-100 hard-disk controller, a PCMCIA interface and a 32-bit RISC processor with digital signal processing capability. It also integrates a servo controller, 65 kbytes of instruction and data cache memory, 500 kbits of buffer memory and VCM and spindle controller and driver, program ROM and uploadable external flash memory. The chip also has extensive power-management and built-in self-test capability. The chip operates with a 3.3-V power supply and has a programmable internal regulator to provide for 2.5-V and 1.8-V power supplies as well.

The read channel megacell implements a high-performance and low-power read/write channel programmable with an operating range of 100 Mbits/second up to 500 Mbits/s, with thermal asperity detection/compensation.

The megacell contains all the functions required for recording digital data on the magnetic media, retrieving data from the analog read-back signal, and for suitably conditioning the servo signals for the servo processor. In addition, the write pre-compensation is programmable.

The three programmable parameters provide customization for each head/media and data zone recording. These parameters include boost control, cutoff frequency and group delay. The dc gain of the filter is independent of the cutoff frequency and the boost. A three-taps cosine equalizer combines with analog-to-digital conversion.

The ATA-100/PCMCIA controller operates at programmable clock rates up to 50 MHz and handles commands from the host and data transfers between the buffer and the host. The hard-disk controller is headerless, with a PCMCIA interface, memory and I/O mode and support and a 500-megabit per second read/write channel. Firmware boots from internal ROM and/or external flash.

A 2-kbyte, two-way associative cache improves firmware execution speed, providing single-cycle (zero-wait-state) execution of code from flash. For critical code — such as interrupt service routine and stacks — 64 kbytes of zero-wait-state RAM is integrated in-chip. Code that is not time-critical but which must be altered may be executed from the data buffer.

The DSP/microprocessor operates at 50 MHz and manages servo, spindle control, hard-disk-controller and other drive functions. The DSP/micro- processor can also utilize a 16-bit instruction set to reduce firmware code size while the 32-bit instruction set will allow for time-critical functions such as servo processing, interrupt handling and long word memory interface.

The automatic CPU wakes on interrupt and an automatic read channel wake/sleep function is combined with other extensive capabilities of the power management block. Additional peripheral blocks like a UART and a serial port interface are incorporated for debug and programming capability.

The servo controller is user-programmable, taking its input from the analog-to-digital converter block of the R/W channel megacell. It has a separate servo frequency synthesizer and the filter has programmable cutoff and boost for servo-mode operation during servo-gate activation.

The Spindle/VCM megacell integrates spindle and VCM controllers as well as power stages. The megacell can operate at a 3.3-V or 5-V power supply level. The megacell includes Master Power On Reset, and a precision low-voltage detection circuit monitors the power supply and initiates VCM retract at voltage fault condition. The on-board programmable regulators provide 2.5-V and 1.8-V power supply based on the requirements of the application. In regular operation mode, it consumes 9 milliamps. The VCM block includes a 14-bit DAC for the servo and R/W function. The load/unload capability is performed under CPU control and is based on a 10-bit DAC.