Custom IC advances see price caps

Custom IC advances see price caps
The close of 2001 couldn't come soon enough for IC companies building application-specific and programmable logic ICs. The communications market upon which they had reaped huge rewards in the past — and which seemed as safe as it was broad-based — has turned on them with such a vengeance that they have yet to experience a real recovery.

As ASIC and FPGA suppliers wait out the dry spell, they are counting on a rollout of new technology offerings to give their customers reasons to keep the new designs coming. More advanced process technology, novel chip architectures, streamlined design flows and better intellectual-property (IP) content will come to the fore this year.

Chip companies will have to operate under greater constraints than they have in the past, however. Equipment vendors were once eager to introduce products ahead of the pack with little regard to cost; today, they're more circumspect. Instead of paying top dollar for a high-end ASIC or field-programmable gate array to meet compressed design deadlines, companies now are taking a hard look at their bill of materials costs, observers said.

These cost concerns have sparked renewed interest in FPGA-to-ASIC conversions. Altera Corp. introduced a mask-programmable gate array that is architecturally similar to its programmable logic parts, a strategy the company expects will continue to gather momentum as companies look to drive cost out of their boards. The biggest benefit is cost. With HardCopy, Altera promises to reduce the size of a functionally equivalent programmable logic device (PLD) by as much as 70 percent.

Other companies are beefing up their FPGA-to-ASIC services as well. AMI Semiconductor (Pocatello, Idaho), which has been doing these conversions longer than most other suppliers,

has tapped Taiwan Semiconductor Manufacturing Co. to shift its conversion service to 0.25 micron and has started pushing to 0.18-micron design rules. Atmel Corp. (San Jose, Calif.) is also getting more active in this area by offering 0.25- and 0.35-micron matrices to convert PLDs from Xilinx Inc. and Altera into ASICs.

Xilinx, which buried its conversion program several years ago, said it has no plans to revive it, and instead is taking a different approach than its crosstown rival Altera. As FPGAs grow more complex, ensuring that ASIC conversions have the same timing as programmable devices becomes too difficult, the company said. Instead, Xilinx will shrink the die size of its FPGA architectures to reduce costs, as it did with its most recent Spartan 2e family. Xilinx also plans to continue to upgrade its Web portal site and develop reference designs to spur more demand for PLDs in markets other than telecom, such as consumer electronics.

Cell-based ASIC suppliers are also showing more sensitivity to the high costs of building high-end ASICs. One of the most significant barriers to entry for this class of device is the cost of the mask set, which can run as high as $700,000 or more at the 0.13-micron technology node. Nevertheless, some companies, such as IBM Microelectronics, the industry's largest ASIC vendor, are exploring ways to provide relief to customers by allowing them to share the mask reticles — a service that foundries have been offering for several years.

If IBM adopts this plan next year as it shifts to 0.13-micron rules, the company could group as many as four IC designs on one reticle — and reduce the price of the mask to about one-fourth of its usual cost. Certain restrictions are inherent in this strategy, though: The size of the four designs should not exceed 10 mm on a side, and customers would have to agree to a fixed schedule for prototype runs, said Tom Reeves, vice president of custom logic for IBM Microelectronics.

The emphasis on lower cost isn't expected to hamper innovation, however. FPGA makers are working hard to find their place in the system-on-chip realm and will continue to develop IP blocks internally and by partnering with third-party suppliers. Altera and Xilinx offer embedded processors that they built from the ground up. As for hardwired CPUs, Altera has announced the availability of an embedded ARM9core, while Xilinx said it expects to introduce in 2002 a PowerPC-based FPGA that it co-developed with IBM.

Indeed, many companies said they are optimistic about the long-term prospects of high-density PLDs. Lattice Semiconductor, which is best known for its in-system-programmable complex PLDs, recently announced its intention to buy Agere Systems' FPGA group. Lattice also announced its intention to introduce by the first half of 2002 an internally developed FPGA.

Market doldrums
It's hard to believe that the market could deteriorate any more than it has in the past 12 months, but 2002 isn't looking too pretty. As of this writing, Lucent Technologies Inc., a key barometer of the telecom industry's health, said its revenue for the final quarter of 2001 would drop 30 percent below expectations. Another bad omen: Merrill Lynch recently stated that equipment sales for 2002 would experience double-digit reduction, according to a survey of telecom carriers worldwide.

That translates into what looks to be a tough year ahead for ASIC and PLD makers. Programmable logic vendors, which until last year had performed relatively well during previous chip industry downturns, stand to lose another 6 percent in revenue. This comes on top of the 36 percent contraction in 2001, bringing revenue down to about $2.5 billion by the end of the year, predicted Gartner Dataquest analyst Bryan Lewis.

The market looks even bleaker for gate array vendors. Revenue from these mask-programmable devices, which continue to be undercut by cell-based ASICs and PLDs, is expected to sputter another 16 percent, compounding the 36 percent decline they experienced last year. This would cut the market for gate arrays down to $1.8 billion next year.

Vendors of cell-based ASICs, which comprise the largest piece of the custom-device pie, may have already seen the worst in their market niche. They have little to look forward to in terms of growth, however. Sales this year will be flat compared with last year, when revenue slid 26 percent to $11.5 billion, according to Gartner Dataquest.

While the market for custom chips is in the doldrums, a few bright spots do exist. One of them is the metro-area-network niche, which some experts expect to snap back this year. IBM's Reeves said, "The thing that will drag on the longest is the core wide-area network. There's been a lot of overinvestment in the core infrastructure, and I don't see a return to growth until at least late '02 and '03."

FPGA/PLD developments are available from the following sources:

http://www.mrc.uidaho.edu/fpga/
http://www.fpga-faq.com/archives/index.html
http://www.chipcenter.com/asic/prod071.html
http://www2.ncsu.edu/eos/project/erl_html/tutorials/asic_dsgn/
http://www.cse.ucsc.edu/classes/cmps222/Spring01/tutor1.pdf
http://www.ecs.umass.edu/ece/fpga2001/
http://www.ra.informatik.uni-stuttgart.de/~rainer/Download/ibm_asic_primer.pdf

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